An Analytical Comparison of Alternative Control Techniques for Powering Next-Generation Microprocessors
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An Analytical Comparison of Alternative
Control Techniques for Powering Next-
Generation Microprocessors
By Rais Miftakhutdinov
ABSTRACT
The latest microprocessor roadmaps show not only ever-increasing performance and speed, but also the
demand for higher currents with faster slew rates while maintaining tighter supply-voltage tolerances.
This topic addresses these challenges by reviewing and comparing various control approaches for
single- and multi-phase synchronous buck converters. An optimized hysteretic control algorithm is
shown offering a significantly improved transient response, which is illustrated with a specific design
example.
core voltage at the battery mode, while keeping
I. INTRODUCTION frequency and voltage higher at performance
mode. In the automatic mode the processor
An unprecedented push in semiconductor continuously adjusts the clock frequency and
technology, especially microprocessors, set the voltage according to system demand. That means
new level of requirements for OEMs [1]. By the the microprocessor voltage regulator must be
year 2005, 3.5-GHz processors having over 190 able to quickly change the output voltage on the
million transistors on chip will consume more basis of the control signals from the system or
then 160 W. The new 0.1-µM technology will microprocessor.
drop the core-voltage of high-performance The other power saving technique called
processors down to 1.2-V range, requiring up to “Intel Mobile Voltage Positioning” or IMVP,
130-A current from the voltage regulator. uses the droop-compensation approach usually
Developing an efficient, low-cost power-delivery associated with the extending of transient
system for that type of load is one of the major window. It also requires the negative core-
problems to be solved. voltage offset for some sleep-mode stages of the
Another problem relates to the high slew-rate microprocessor [18]. This approach extends the
current transients, exceeding 40,000 A/µs battery life, because power dissipation of the
through the die when a processor abruptly microprocessor is inversely proportional to core
changes its operation state. Obviously, special voltage square. These new requirements must be
packaging, high-frequency decoupling, and a fast counted during power-delivery system design.
transient-response regulator must be used to keep A controller IC is a significant part of the
the core-voltage tolerance within the required microprocessor power supply: it integrates the
few percent. described power-saving functions. Still, the main
Additionally, the latest mobile processors goal of controller is to provide an accurate output
have implemented special power-saving voltage at steady-state conditions and fastest
technique called SpeedStep , PowerNowTM, and
TM
response with minimum voltage tolerance at high
LongRunTM [15-17] trying to prolong battery life. In slew-rate transients. The topic of this article
accordance to this technology, the explains the control-approach influence on
microprocessor has different modes of operation; transient and optimal power-delivery system
i.e., “performance,” “battery” and “automatic.” design.
The idea is to decrease the clock frequency and
1-1Review of available literature shows that the limitations of actual controllers (such as
usually the authors provide rule-of-thumb delays, fixed on- or off-time, compensation
recommendations for selecting different bandwidth, and error-amplifier saturation) that
components on the basis of transient might degrade the transient response. A review
parameters [5-7,13]. This topic discusses the and comparison of control techniques shows that
transient in a power-delivery system as a whole, a hysteretic regulator is one of the most
thereby suggesting more accurate design appropriate solutions for powering
procedure. It includes the model selection, the microprocessor-type loads having high slew-rate
derivation of transient equations in the time and amplitude transients.
domain, the observation of transient waveforms, A hysteretic controller and its modifications
and the effect of different system parameters, are described in the next section. Although a
including parasitics and controller characteristics. hysteretic regulator has been used in power
This approach defines the worst condition of electronics for a long time [28], earlier
transient, which is determined by the moment publications do not address modern applications
within the switching cycle in which the transient and conditions. This analysis includes new
occurs. This condition is not described in the equations for the switching-frequency
literature, although it influences component calculation, both for the typical hysteretic control
selection. This topic addresses the popular and for its modifications [26,30,33,34,40,42]. Finally, a
synchronous buck converter and the multi-phase design example and the optimization procedure
(interleaved) topology based on it. The equations are provided to implement the analysis results
for a required number of output bulk capacitors and to address important practical issues.
are derived and an optimization procedure for the
output filter design is suggested both for one- and II. TRANSIENT ANALYSIS
multi-phase topologies.
The next section of the topic reviews and A. Power Distribution Model
compares different control approaches most The model selection for an analysis is always
suitable for microprocessor power supplies. On a tradeoff between practicality and accuracy of
the basis of the previous transient analysis, it first the results. Fig. 1 shows the power distribution
formulates a control algorithm for the best system considered in the analysis.
transient response. The next step explains how
Lo uP or DSP
+ vA Rb Lb vB with HF decoupling
D ESR Load current
Vin 1-D ESL
Chf
Die
Cdie
or
Co
_
Driver Hyst.
_ Comp.
Q _
Q +
Vref
Fig. 1. Analyzed power-delivery system at load-current transients.
1-2The model includes the synchronous buck B. Analysis Approach
converter, the output inductor LO, the output bulk There are many publications where dc-to-dc
capacitor with parasitics, and the power supply buck converters for powering microprocessor are
traces between the bulk capacitor and the considered at load-current transients [19-24,26,30-
34,37,40,42,44-46]
package or cartridge of the microprocessors. The .
output bulk capacitor is presented as a series Computer simulation is one of the popular
connection of an equivalent ideal capacitor CO, technique for the transient analysis [20]. It is a
with equivalent series resistance ESR and useful tool for design validation, but it does not
equivalent series inductance ESL. The equivalent reveal analytical relations among the parameters
resistor RB characterizes the resistive voltage of a power-delivery system. Therefore, it is
drop through the supply paths and is the difficult to predict and find the optimal solution.
summarized resistance of the traces and the Small-signal analysis is another technique
[21,22]
connectors. The equivalent inductor LB . Some authors optimize the small-signal
characterizes the inductive voltage drop across frequency characteristics—for example the
the traces and connectors. The high-frequency output impedance [22]. However, this practice is
decoupling capacitors on the die CDIE and inside questionable, because it applies the small-signal
the package CHf are not included in the analysis, analysis to the large-signal transient process. This
because usually the load-current slew-rate is topic shows that small-signal analysis cannot
specified at the package pins. Nevertheless, in explain the dependence of transient upon the
situations when LB and ESL are too high, it is moment within a switching cycle when it occurs.
important to decrease the slew-rate of current Assuming that a load-current transient is a
through the bulk capacitor CO by adding the high- linear function of time, the equations are derived
frequency decoupling capacitors around the for the voltages and currents of all components of
package. This procedure is also described in the power-delivery system as a function of time
transient analysis section.The analyzed model is before, during, and after the load-current
the lumped one, while in an actual power- transient. These equations are included in a
delivery system the output capacitors and MATHCAD-based software program to view the
parasitics are distributed over the PCB board transient voltage and current waveforms. The
area. But results of the analysis using this model same equations also characterize peak values of
are confirmed by the measurements and the transient. On the basis of these equations, the
sufficiently accurate for most applications. The curves for selecting the optimal output filter and
same model of the power-delivery system is the minimum number of bulk capacitors selection
suggested in Intel's Power Distribution are built [26,30,33,34,40,42].
Guidelines [5-7]. The controller and the drive
circuitry are assumed not to have any delays. C. Transient Waveforms and Experimental
They are able to maintain the on- or off-state of Verification
the related power switch during the transients as Fig. 2 shows the waveforms across the
long as necessary to return the output voltage different elements of the model (Fig. 1) at the
back to the steady-state level as soon as possible. load-current step-down.
In this case, the controller does not degrade the The output current changes between IO(max)
transient response, which is determined by and IO(min) (Fig. 2a) with a constant slew-rate. The
passive components only. The hysteretic step-up transient waveforms have the same stages
controller in Fig.1 includes the comparator with a and are qualitatively similar to a step-down,
hysteresis window, the reference voltage, and the although they are described by different
drive circuitry with a complementary control of equations.
high- and low-side FETs. Fig. 1 is an example
only, but it will be shown later that it is a good
approximation of the ideal controller.
1-3CDIE
with decoupling
uP or DSP
DIE
CHF
vB
Load Current
or
LB
VREF
RB
vA
+
–
+
–
+
–
Comp.
Hyst.
ESR
CO
ESL
LO
Driver
Q
Q
VIN +
–
VIN
t
t
t
t
t
t
Trecov
IOMIN
VmC
ms
VmL
t
VmR
Textr
Vm2
TO
IOMAX
Vm1
0.16
V
iO, iL
iC, vCO
vA
(e) vESR+vRb
vB
(d) vESL+vLB
(b)
(a)
(c)
(f)
(a) Load-current and output inductor current transient waveforms.
(b) Transient-voltage waveform on the output of the dc-dc converter (point A in Fig. 1).
(c) Transient-voltage waveform on the microprocessor package pins (point B in Fig. 1).
(d) Transient-voltage waveform at the inductive components of the model ESL and LB.
(e) Transient-voltage waveform at the resistive components of the model ESR and RB.
(f) Transient-voltage waveform and current on the-capacitor CO.
Fig. 2. Waveforms through different elements of the model during load-current step-down transition.
1-4To verify the derived equations, the on an ideal controller without delays, and
MATHCAD transient waveforms are compared measured waveforms, with the switching
with the measured ones under the same regulator based on the hysteretic controller
conditions. As shown in Fig. 3, the theoretical TPS5210, shows that the hysteretic control,
and measured waveforms are very close for the despite typical 250 ns delays does not degrade
load-current step-down and step-up conditions. the transient characteristics significantly.
The comparison of analyzed waveforms, based
VA(50mV/div), IO(14.5A/div)
0 10 20 30 40 50 60
Time (microseconds)
(a) Theory ( b) Measurement
VA(50mV/div), IO(14.5A/div)
0 10 20 30 40 50
Time (microseconds)
(c) Theory (d) Measurement
Fig. 3. Theoretical (a), (c) and measured (b), (d) waveforms at load-current step-down (a), (b) and step-
up (c), (d)transitions. [The theoretical waveforms show the output voltage (top) and load-current
(bottom) transients.The measured waveforms include VDS voltage of the low-side FET (Ch1: 20V/div),
output voltage (Ch4: 50mV/div) and load current (Ch3: 14.5A/div)].
1-5D. The Two Extreme Values of a Transient
Fig. 4 shows typical load-current transient
VA(50mV/div), IO(14.5A/div)
waveforms. The output-voltage waveform has
two extreme values, VM1 and VM2.
For most applications the transient slew rate
of the load current is much higher than the slew
rate of the output-inductor current. Therefore, the VM1
first peak, VM1, depends mainly on the parasitics VM2
of the output capacitor and supply path. The
controller transient-response characteristics
(Fig.5a) do not affect it significantly. The second
peak, VM2, depends on the resistive components Fig. 4. Typical load-current transient waveforms.
ESR and RB, the capacitive component CO, the
inductor value LO and the converter
characteristics, including the switching frequency
and the type of control (Fig.5b).
V M1
VM1 V M2
VM2
Lo uP or DSP Lo
Lb Lb
uP or DSP
+ vA Rb vB with HF decoupling
+ vA Rb vB with HF decoupling
D ESR Load current ESR
D Load current
Vin 1-D ESL
Chf
Die
Cdie 1-D Chf Cdie
or Vin ESL Die
or
Co Co
_ _
Driver Hyst. Driver Hyst .
_ Comp. _
_ Comp. _
Q Q
Q + Q +
Vref Vref
(a) (b)
Fig. 5. Different parameters and their effect on peaks VM1 and VM2.
1-6III. IMPACT OF SYSTEM PARAMETERS ON A
TRANSIENT
VA(20mV/div), IO and IL(10A/div)
A. Output Inductor Value
It could be thought, that the lower output
inductor value enables better transient-response
characteristics because of a faster inductor-
current change to the new level after the load-
current transient occurs.
In reality, the example in Fig. 6 shows that,
after some optimal value (Fig. 6b), further
decreasing of the inductor value increases the
0 5 10 15 20 25 30 35 40 45 50 55 60 65
peak-to-peak transient amplitude because the
Time (microseconds)
output ripple rises significantly. As shown later,
the optimal inductor value depends on the (a) LO = 1.6 µH VO(max) = 79 mV TRECOV = 34 µs
switching frequency and the characteristics of the
output bulk capacitors.
VA(20mV/div), IO and IL(10A/div)
B. Dependence on Switching Cycle Position
The output-voltage transient response
depends on where the load-current transient
occurs within the switching cycle. If the load
current steps down, the excessive energy stored
in an output inductor is delivered to the output
capacitor. The worst case for the step-down
transition occurs if the transient takes place at the
end of a conduction time of high-side FET,
because the inductor current is at its maximum. 0 5 10 15 20 25 30 35 40 45 50 55
At that moment the inductor stores the maximum Time (microseconds)
energy, while the output ripple voltage also is at
its maximum. So the effect of transient is most (b) LO = 0.8 µH VO(max) = 62 mV TRECOV = 19 µs
significant at that moment, causing greater output
voltage spikes than at any other moment (Fig. 7).
VA(20mV/div), IO and IL(10A/div)
In contrast, the worst case for the step-up
transition occurs if the transient happens at the
end of the switching cycle, because the inductor
current and output voltage ripple are at their
minimum at that moment. Only the output
capacitor supplies the load during the step-up
transient, while the inductor must restore its
energy and current to the new load-current level.
This fact cannot be described with small-signal
analysis, although the effect must be considered
for reliable output filter selection. 0 5 10 15 20 25 30 35 40 45 50
Time (microseconds)
(c) LO = 0.4 µH VO(max) = 72 mV TRECOV = 12.5 µs
Fig. 6. Transient waveforms for different
inductor values LO.
1-7IV. EQUATIONS FOR THE REQUIRED NUMBER
VA(20mV/div), IO and IL(10A/div)
OF CAPACITORS
The peak values VM1 and VM2 for the worst-
case step-down and step-up transients can be
found with the derived equations.
(See Appendix 1.) Assume that the output filter
capacitors are connected in parallel and that each
capacitor has the characteristics CO1, ESR1 and
ESL1. The number 1 after a parameter means that
the parameter relates to one of many capacitors
0 5 10 15 20 25 30 35 40 45 50 connected in parallel. The literature shows
[33,34,42]
Time (microseconds) that if ∆VREQ is the maximum allowable
peak-to-peak transient tolerance, then the
(a) Worst case: Transient occurs at the end of the upper
FETs conduction time. required number of output bulk capacitors N1
and N2, to meet the conditions VM1 = ∆VREQ and
VM2 = ∆VREQ, respectively, can be found by
VA(20mV/div), IO and IL(10A/div)
equations (1) and (2):
where KL = ∆ILEQV/∆IO (3)
or
VOUT ⋅ (1 – D ⋅ n )
KL = (4)
L OEQV ⋅ ∆I O ⋅ f S ⋅ n
The parameter m depends on the type of
transient. It is equal to:
m =1– n⋅D (5)
for the worst-case step-down transient and to:
D ⋅ (1 – n ⋅ D )
m= (6)
0 5 10 15 20 25 30 35 40 45 50
Time (microseconds) n ⋅ (1 – D )
(b) Best case: Transient occurs at the end of the switching
cycle.
Fig. 7. Output voltage (bottom curve) and
inductor current (dashed) waveforms for the
different instants when the load-current (top,
solid) step-down transition occurs.
ESR1 T æ TO ö æ TO ⋅ f S ⋅ n ö
+ ESR1 + O + çç ESR1 + ÷ ⋅ ç1 – ÷ ⋅ KL
TO 2C O 1 è 2 ⋅ C O 1 ÷ø è m ø
N1 = (1)
∆VREQ L B
– – RB
∆I O TO
1é m TO æç ESR12 ⋅ C O 1 ⋅ f S ⋅ n m ö
÷ ⋅ KL + m 1 ù
ê – + ESR1 + + ⋅ ú
2 ê C O 1 ⋅ f S ⋅ n C O 1 çè m 4 ⋅ C O 1 ⋅ f S ⋅ n ÷ø C O 1 ⋅ f S ⋅ N KL ú
N2 = ë û (2)
∆VREQ
– RB
∆I O
1-8for the worst-case step-up transient. The Assume that RB = 1.5 mΩ; LB = 1.0 nH;
∆ILEQV is the peak-to-peak ripple portion of the ∆IO = 23.8 A; vIO = 20 A/µs and TO = ∆IO/vIO =
output inductor current, ∆IO is the load-current 1.2 µs in accordance with the VRM 8.4
step, D = VOUT/VIN is the duty cycle, fS = 1/TS is requirements [10]. Then the voltage drop through
the switching frequency, and TS is the switching the supply path is:
cycle. The number of channels in an interleaved VB = 35.7 mV+20 mV = 55.7 mV (11)
(multi-phase) regulator is n. For the one-channel For the 1.65-V output power supply, the
converter n = 1. Later discussion shows that, with voltage drop is almost 3.8%. This example shows
some assumptions, the same transient analysis why it is important to keep the output filter
applies to the one- and multi-channel interleaved capacitors as close as possible to the
converters. microprocessor package to avoid a significant
The second peak VM2 exists only if the voltage drop due to supply path parasitics.
following condition is fulfilled: Let us consider the other example. The
m æ 1 1ö expression:
⋅ç + ÷ – ESR ⋅ C O > TO (7)
f S ⋅ n è KL 2 ø æ ∆VREQ ö æ L B 1 ö
ç ÷ − çç ÷÷ − R B 1
where TO is the load-current transition time. ç ∆I ÷ T
è O ø è O ø
If this condition is not fulfilled, only the first is the denominator of the Equation 1.
spike and Equation 1 must be considered. The Obviously, the minimum number of bulk
other assumption of the analysis is that TO < capacitors N1 can be calculated only if the
D·TS. This assumption does not restrict the following inequality is met:
analysis for most applications. Equations 1 and 2 ∆VREQ L B1
can be used for the optimal output-filter design > + R B1
based on the optimization curves N1 = N1(fS, ∆IO TO
LO(eqv), n) and N2 = N2(fS, LO(eqv), n). But first, let Assume that ∆VC = 96 mV for the previous
us consider some simple but useful relations from example.
these equations. In this case ∆VREQ / ∆IO = 4 mΩ. This is an
important transient characteristic, let’s call it
A. Influence of Supply-Path Parasitics Equivalent Transient Resistance (ETR). LB/TO =
The voltage-transient waveforms on the 0.84 mΩ. That means that the supply path
converter output pins (point vA in Fig.1) and on parasitics LB and RB give us 4 mΩ/(4 – 0.84 –
the microprocessor package supply pins (point 1.5) mΩ. = 4/1.66 = 2.4 times number of
vB in Fig.1) are different because the supply-path capacitors increase.
resistance RB and inductance LB cause an
additional voltage drop. If the output current step B. Bulk Capacitor Parameters
∆IO and slew-rate vI are defined as: ESL
ESR
To
∆IO = IO(max ) – IO(min ) (8) The expression To 2 .Co
is part of the
∆I O numerator of the Equation 1 for N1. It
vI O = (9) characterizes the selected capacitor
TO characteristics. For example, the aluminum
then the additional voltage drop VB of the electrolytic capacitor 6.3ZA1000 from Rubycon
supply paths is: has ESL = 4.8 nH, ESR = 24 mΩ and CO =
VB = VR B + VL B = ∆I O ⋅ R B + vI O ⋅ L B (10) 1000 µF. That gives us 4.8 nH/1.2 µs +24 mΩ
+1.2 µs /(2•1000 µF) = (4+24+0.6) mΩ =
28.6 mΩ. After substituting 1.66 mΩ for
denominator from the previous example:
28.6 mΩ /1.66 mΩ = 17.2
1-9Roughly at least 17 capacitors must be used There are two different approaches for a
to meet the requirements. It will be shown later practical implementation of this idea. Fig. 9a
how this number can be reduced by additional shows the simplest way called "passive" droop
high-frequency decoupling. compensation. The droop resistor RD = ESR is
inserted between the output capacitor and the
C. Active and Passive Droop Compensation output voltage sense point VA. Passive droop is
Equations 1 and 2 show that increasing fast and naturally follows the load-current
∆VREQ can lower the required number of bulk transient. This approach can be used probably
capacitors. The droop compensation is an with any type of control technique. The drawback
effective technique to increase ∆VREQ. Droop is that it requires the additional resistor with
compensation means that the dc output voltage of power losses in it. The other approach, called
the converter is dependent on the load. It is set to "active" droop compensation, is shown in
the highest level within the specification window Fig. 9b. It can be implemented by adding an
at no-load condition and to the lowest level at offset proportional to the output current, which is
full-load. This approach degrades the static load subtracted from the reference voltage, or by
regulation but increases the output-voltage changing the dc gain and the compensation
dynamic tolerance by as much as twofold, thus circuitry to get a desirable output impedance
reducing the number of bulk capacitors required. ZOUT [22,37]. The main challenge here is that it
For the same output filter, this technique allows a must be accurate and fast enough to follow the
decrease in peak-to-peak output-voltage transient transients having their own repetition frequency
response. Fig. 31 in the design-example section up to 100 kHz [8-11].
shows the output voltage budget with droop The transient waveforms with and without
compensation. active droop compensation are shown in Fig. 10.
The popularity of droop compensation is One can see that without droop compensation
confirmed by the fact that it has numerous names (Fig. 10a) the output-voltage peak-to-peak
such as "Programmable Active DroopTM,” amplitude is 146 mV and it exceeds the
"Active Voltage Positioning,” "Adaptive Voltage requirements, as shown by the cursors. With
Positioning,” "Summing-Mode Control,” "Intel droop compensation (Fig. 10b), the peak-to-peak
Mobile Voltage Positioning (IMVP),” etc. transient is only 78 mV, keeping the output
voltage of the same regulator well within the
requirements.
1-10Passive droop resistor
LO
LB
VA RD + RB VB
ESR Load current
D
VIN 1-D ESL or mP
CO
_
_ Driver Controller
Q _
Q
+
Vref
(a) Passive droop compensation
LO
VA + RB LB VB
D ESR Load current
VIN 1-D ESL or mP
CO
_
Driver
_
Q _
Q Controller
+
VREF
Change DC gain and
compensation to get
required ZOUT
(b) Active droop compensation
Fig. 9. Passive (a) and active (b) droop compensation technique.
(a) Without droop compensation Vout p-p = 146 mV (b) With droop compensation Vout p-p = 78 mV
Fig. 10. Active droop compensation technique. Channel 2 shows the output voltage (50 mV/div.),
Channel 3 shows the load current (10 A/div.), and the cursors show the required limits for the output
voltage.
1-11decoupling capacitors very close to
D. Optimization Curves microprocessor pins.The equations for N1 and
Equations 1 and 2 for the required numbers of N2 can be drawn as a function of TO = ∆IO /vIO
bulk capacitors N1 and N2 can be used to build for the selected inductance LO = 2 µH and
optimization curves as a function of the output switching frequency fS = 100 kHz (Fig.12).The
inductance LO (Fig.11). graph shows that doubling TO from 1.2 µs to
These curves are built for a step-down 2.4 µs will decrease the number of bulk
transient by using aluminum electrolytic capacitors from 20 to 15. This transient time
capacitors with: increase means that the slew-rate of the transient
CO = 1000 µF, ESR = 24 mΩ, ESL = 4.8 nH must be decreased from 20 A/µs to 10 A/µs. A
with the following conditions: solution by adding high-frequency ceramic
VIN = 5 V, VOUT = 1.65 V, fS = 100 kHz, ∆VOUT decoupling capacitors is illustrated in Fig.13. For
dc = -80 mV / +40 mV, ∆VOUT ac = -130 mV / 15 electrolytic capacitors the total inductance is
+80 mV, IO(max) = 26 A, IO(min) = 2.2 A, ∆IO = ESL1/15 + LB = 4.8 nH/15 + 1 nH = 1.3 nH. The
23.8 A, ∆VREQ = 96 mV, 805 1-µF ceramic capacitor has ESL1 = 2.6 nH
vIO = 20 A/µs, TO = 1.19 µs, RB = 1.5 mΩ, LB = including inductance of vias and traces. The
1 nH. equivalent inductance of four capacitors placed
The higher number of capacitors related to very close to the microprocessor is
the curves N1 and N2 must be selected to meet 2.6 nH/4 = 0.65 nH. Adding four high-frequency
the requirements—in this case for LO = 2 µH, N1 decoupling capacitors roughly halves the slew-
= 20, while N2 is only 12. These values mean rate, in accordance with the following equation:
that the voltage drop associated with ESL and LB vIO new = vIO ⋅ (0.65 nH/1.3 nH) = 20 A/µs ⋅ 0.5
is too high. The influence of ESL and LB and the = 10 A/µs.
required number of bulk capacitors N1 can be
decreased by placing the high-frequency
24 30
22 28
26 20 caps
20
Number of Capacitors (N1 and (N2)
Number of Capacitors (N1 and (N2)
24
18 22
16 20 N1
15 caps N1
18
14 Curve N1
(relates to peak Vm1) 16
12
14
10 12
Curve N2
8 (relates to peak Vm2) 10
8
6 Peak Vm2 does not exist in this area at t>TO.
6 N2
4
1 ∆ Io 4
Limitation: ESR . Co > m . Ts . To
2 2 ∆ IL 2
0 0
0 1 2 3 4 5 6 7 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
µH)
LO (µ Transient Duration, TO
Fig. 11. Optimization curves for the required Fig. 12. Required number of bulk capacitors N1
number of bulk capacitors based on the equations and N2 as a function of the transient duration TO.
for N1 and N2.
1-12This decrease in the slew rate means that output filter selection procedure for the
adding four high-frequency ceramic capacitors interleaved regulator at high slew-rate load-
close to the microprocessor pins decreases the current transients. Apparently the analysis and
number of bulk capacitors from 20 to 15. Fig. 12 optimization procedure for the one-channel
shows that further decoupling does not give synchronous buck converter can be extended to
significant effect, although four more ceramic the multi-phase interleaved synchronous buck
capacitors might save roughly two more bulk converters.
capacitors. The capacitance and ESR of the The power-delivery system considered in the
ceramic capacitors must be big enough to support analysis appears in Fig. 14. The analyzed model
the load until the bulk capacitors will take over includes the n-channel interleaved synchronous
the transient. buck converter. Each channel of the model is
similar to the one-phase solution analyzed earlier
V. TRANSIENT RESPONSE OF A MULTI-PHASE (Fig.1).
INTERLEAVED BUCK CONVERTER The converter operates in a phase-shifted
manner at the steady state condition sharing the
The interleaved synchronous buck converter current equally between the channels. For the
becomes a popular solution to supply high- best response during the transients, all channels
current microprocessors because of the lower turn the high-side FETs simultaneously on at
input and output current ripple and the higher load-current step-up or off at step-down, thus
operating frequency of the input and output allowing the fastest recovery and a minimum
capacitors compared to the one-channel solution dynamic tolerance of the output voltage. The
[42-46]
. Interleaving also enables spreading of the control signals do not have delays and the duty
components and the dissipated power over the cycle covers all possible ranges from zero to one.
PCB area, but it requires equal current-sharing When the output voltage returns to the nominal
between the channels. Different control level after the transient, the channels resume
approaches to achieve accurate current-sharing phase-shifted operation with the same sequence
and fast transient response for interleaved they had before the transient. This ideal control
microprocessor power supplies are suggested in algorithm for the best transient response is
the literature [44-46]. Meanwhile, outlining an illustrated in Figs. 14 and 15.
optimal application area for the one-channel and
interleaved solutions requires an analysis and
µs
10-100A/µ µs
100-1000A/µ µs
>1000A/µ
Voltage
System IO
Regu-
Power I3 I2 I1
Supply
Lator
Bulk Decoupling Packaging Die
Capacitance Capacitance Capacitance Capacitance
æ ∆I ö æ ∆I ö L
Roughly: ç ÷ ≅ç ÷ × N −1
è ∆t ø N è ∆t ø N −1 LN
Fig. 13. How high-frequency decoupling decreases current slew-rate.
1-13LO LB uP or DSP with
+ VA RB VB HF decoupling
D ESR Load current Chf Cdie
VIN 1-D ESL Die
or
CO
_
Driver
_ Controller
Q
Q
Channels
2 ... (n-1)
Steady-state
control signals
LN
D
1-D Control signals
during transient
Driver
_
Q
Q
Fig. 14. Analyzed model of the interleaved synchronous buck converter.
D x TS TS The analysis is based on the same approach
(1-D) x TS
described earlier for the one-channel synchronous
Control: Ch. 1 buck converter. Assume that (1-D) > n·D, where
n - number of channels and D =VOUT/VIN - duty
Control: Ch. 2
cycle of each channel. This condition is fulfilled
for most microprocessor power supplies, for
IL: Ch. 1
example, the popular 12-V input and 1.6-V
∆IL output synchronous buck converters with four
IL: Ch. 2
channels have D = 0.13, (1-D) = 0.87, n·D =
(1-Deq) x TSEQ 0.52, and thus 0.87 > 0.52. It can be shown that
Deq x TSEQ
IO, the summarized current through the inductors and
IL:Ch. 1+Ch. 2 TSEQ output capacitor of an n-channel interleaved
∆ ILEQ converter has the same waveforms as an
IC equivalent one-channel converter with the
following parameters:
Fig. 15. Control signals, inductor currents DEQV = n·D, fS(eqv) = n·fS, TS(eqv) = TS/n, LO(eqv)
through the each channel and summarized = LO/n, VIN(eqv) = VIN/n, ∆ILEQV = ∆IL·(1-
inductor, capacitor and load currents of n·D)/(1-D)
interleaved buck converter at load-current step-
down transient.
1-14where D is duty cycle, fS is switching The transient-response dependence on the
frequency, TS is switching period, LO is output position of the switching cycle in which the load-
inductor, VIN is input voltage and ∆IL is peak-to- current transient occurs is the same as that of the
peak inductor-current ripple of each channel of one-channel converter. The difference is that the
the interleaved buck converter. DEQV, fS(eqv), summarized currents through all the channels and
TS(eqv), LO(eqv), VIN(eqv), and ∆ILEQV are duty cycle, the output voltage ripple cancellation effects
switching frequency, switching period, output must be considered, which is accomplished in
inductor, input voltage and peak-peak inductor- this analysis by substituting an equivalent one-
current ripple of the one-channel equivalent buck channel converter. Further analysis estimates the
converter respectively. The waveforms in Fig.15 worst-case transient and compares the different
illustrate this statement. type of output capacitors in the interleaved
During the transients, because all channels converter.
turn to the same state simultaneously in The example below illustrates how the
accordance with the proposed control algorithm, number of channels and capacitor characteristics
the interleaved converter can be considered a defines the number of required bulk capacitors
one-channel, which now has the same input N1 and N2 [42]. The following requirements are
voltage VIN as the original interleaved one and typical for a modern high-end microprocessor:
the output inductor LO/n. The consideration of the
parameters of the equivalent one-channel • VIN = 12 V,
converter helps to explain what kind of • VOUT = 1.5V,
advantages to expect from the interleaved • IO(max) = 50 A,
converter. Interleaving provides the same • IO(min) = 0 A,
properties as the one-channel converter when • ∆IO = 50 A,
operating at higher frequency, having higher duty • ∆VREQ = 100 mV,
cycle and lower input voltage and inductor value. • vIO = 50 A/µs,
But all this happens only if a good steady state • RB = 0.4 mΩ,
and dynamic current sharing are provided • LB = 0.2 nH,
between the channels. • fS = 200 kHz.
In an ideal control circuit, the transient Optimization curves are built for aluminum
response of the interleaved converter is defined electrolytic, OS-CON, specialty polymer SP and
by the output-filter characteristics including the ceramic capacitors. The required number of
slew-rate of the inductor current. It is interesting capacitors N2 and inductor value LO at different
that for the step-down transient when all low-side switching frequencies for this application are
switches are turned on, the inductor-current slew shown in Table 1.
rate equals (VOUT·n)/LO and has the same slew- These numbers of capacitors relate to an ideal
rate as during the (1-DEQV)-part of the switching controller. The practical implementation might
cycle. But for the step-up transient when all high- require some additional capacitors. But this
side switches are turned on, the slew-rate of the analysis sets goals to achieve and shows relations
inductor current is (n·(VIN-VOUT))/LO, which is between the number of capacitors and number of
much higher than in steady state operation during channels, switching frequency, inductor value,
the DEQV-part of the switching cycle, where the and capacitor and layout parasitics.
slew-rate is only (VIN-VOUT·n)/LO.
1-15TABLE 1. OPTIMAL REGULATOR PARAMETERS FOR DIFFERENT TYPES OF CAPACITORS AND NUMBER
OF CHANNELS
FS Parameters of each Number of Capacitors for Different Numbers of
per capacitor Interleaved Channels / LO per Channel
Type Vendor Part Number ch CO ESR ESL 1 one 2 two 3 three 4 four
lkHz 1µF 1mΩ 1nH Channel Channel Channel Channel
Aluminum
Rubycon 6.3ZA1000 200 1000 24 4.8 18/0.8µH 16/1.6µH 16/2.4µH 15/3.2µH
Electrolytic
OS-CON Sanyo 4SP820M 200 820 8 4.8 8/0.25µH 7/0.5µH 6/0.75µH 6/1.0µH
Specialty
Panasonic eefcd0d101r 300 100 20 3.2 28/0.1µH 18/0.2µH 15/0.3µH 13/0.4µH
Polymer
Ceramic, grm235y5v
Murata 400 22 20 0.5 60/0.05µH 30/0.1µH 20/0.15µH 16/0.2µH
1210 226z10
The following is the summary of the
comparison. VI. CONTROL TECHNIQUES FOR POWERING
• The aluminum electrolytic and OS-CON LOW-VOLTAGE, HIGH SLEW-RATE LOAD
capacitors require significant additional high
frequency decoupling at slew-rate 50 A/µs A. Review of Control Techniques for High-Slew
because N1 >> N2. Rate Load-Transient Applications
Different control approaches are considered
• Interleaving for aluminum electrolytic and in the literature [19-27,30,33,37,40,41,45,46] for the high-
OS-CON capacitors does not significantly slew-rate load-current transient applications.
decrease the number of required output Some solutions require additional circuitry, such
capacitors. Only the decrease in the input as a power amplifier or switch, to regulate the
filter ripple needs to be considered as the output voltage if it exceeds some set points at the
result of interleaving. transients [23,25]. This approach complicates the
• The 2-channel interleaving is optimal for the design. Moreover, to avoid the interaction
specialty-polymer capacitors. They require between the main and the additional control
much lower high-frequency decoupling at circuitry at normal operation, the output voltage
50 A/µs load-current slew-rate in comparison set points of the additional circuitry have to be at
with the aluminum electrolytic capacitors. least 2-3 percent different from the reference
voltage of the main circuitry. This requirement
• The most significant effect of interleaving causes some delay until the additional circuitry
relates to the solution with the ceramic starts to control the output voltage when the
capacitors. The required number of them transient occurs. The cost of this delay is the
drops almost inversely proportional to the additional bulk capacitors in the output filter. The
number of interleaved channels. Ceramic other potential problem results from the
capacitors do not require additional occurrence of the transients in the
decoupling at 50 A/µs load-current slew-rate. microprocessors with high repetitive frequency
(up to 100 kHz most of their operation). That
means that this additional circuitry could operate
frequently and dissipate a significant amount of
power, because it usually operates in the linear
mode. Although these ideas are interesting and
1-16may find their optimal application niche, this • The compensator senses the change of the
topic addresses only the control approaches that output voltage when the load-current transient
do not require additional switches or power occurs. The tight tolerance requirements for
amplifiers. the output voltage makes it even more
Let us review some basics of the control difficult to separate the output voltage change
theory before considering and reviewing different caused by a load-current transient from noise.
control approaches. In control theory, any
switching regulator with feedback loop includes a • The direct sensing of the load current helps to
plant and a compensator. The plant in a switching avoid the additional delays. The load current
regulator is its power stage, with at least two must be sensed between the output capacitor
different states controlled by the switching and the microprocessor because the output
function. The regulated output signal of this inductor current or current through the power
control system is the output voltage of the switch is not the actual load current.
regulator. The compensator senses the output • The ESR and ESL of the output capacitors
voltage and somehow changes the switching and the supply path parasitics help to sense
function to keep the output voltage within the the load current and its changes because of
required window. The power stage of the voltage the additional voltage drop. But the design
regulator must include a low-pass filter, which is goal is to avoid this voltage drop by selecting
a second order L-C filter in the applications lower ESR and ESL capacitors and
considered. There are many different improving the layout. These are also
disturbances, such as input voltage, temperature, contradictory requirements.
aging, and load current that change the output
voltage. But for the considered power-delivery • The compensator cannot improve the
system with a high-slew-rate transient type of dynamic characteristics of the power stage.
load, the main disturbing factors is the load Actually the compensator only degrades the
current and the slew-rate of the current transient. transient response because of the delays and
As discussed in the "Introduction" section above, restrictions put by the compensator on the
the load-current transient step and its slew-rate power stage.
for the considered type of load is much higher • Some think that the compensator has no
than in most generic applications. At the same influence and that only the output capacitor
time the required tolerance of the output voltage characteristics define the response
of the regulator is very tight. On the basis of this characteristics because the slew-rate of the
discussion the following main problems can be transient is too high. That might be true if the
specified: output capacitance is so over-killed that any
• The low-pass filter nature of the power stage controller is fast enough to handle the
means that the fast response to the load- transient. In reality, an output filter with
current transients is limited and defined first minimum size (or cost) can be designed only
of all by the power stage itself. by using a fast and optimal compensator
(control approach). In other words, the sooner
• The power stage with a fast response to the
the controller starts to react on the transient,
load-current transient might require high-slew
the better is the response, because the first
rate current changes through its own
spike can be suppressed by high- or mid-
components. At the same time the power
frequency decoupling.
stage must prevent the transient propagation
outside the regulator without a significant
increase of the input filter. These are
contradictory requirements.
1-17This discussion suggests the desirability of
+ +
first finding the optimal power stage, including VIN
D
1-D
VOUT
the low-pass filters. (That attempt was made in _ _ RLOAD
the previous section.) After that, on the basis of
Error Amp
the transient analysis, the control approach must Z1
COMP _ Z2
be selected. The control approach must not _Driver Latch +
Q +
significantly degrade the dynamic characteristics Q Q
R _
S VREF
of the power stage and must provide some
additional properties that increase the reliability OSC
and the robustness of the power-delivery system,
for example, current limit, constant or variable
switching frequency, and pulse-duration Fig. 16. Voltage mode control.
limitations.
ISENSE
There is a large variety of control techniques
in power electronics. The control techniques + +
D 1-D VOUT
reviewed and considered in the topic are selected VIN
_ _RLOAD
on the basis of their current popularity in this
application area or of their promising Error Amp
Z1
characteristics. These control approaches are _ Driver Latch Comp _ R
voltage mode (Fig. 16), peak current mode (Fig. Q R
+
_+ +
17), average current mode (Fig. 18), V2-mode Q Q
S VREF
Sloop Comp
(Fig. 20), and hysteretic (ripple) mode (Fig. 19). for D>0.5
They can be divided in the following two groups: OSC
• Control techniques that do not sense the load
current or its changes directly, and so do not Fig. 17. Peak current mode control.
feed-forward or feed back this signal. This is
ISENSE
group-control with a “slow” feedback loop,
because it senses the disturbance caused by +
D
+V
OUT
VIN 1-D
the load current indirectly and uses this signal _ _RLOAD
in the main feedback loop. This group R2 Current Amp
Error Amp
improves the dynamic response by increasing Z1
Comp _
the unity-gain-frequency bandwidth of the _ Driver Latch _ Z2 _ R
Q _S +
voltage mode [20] or of different types of Q QR + +
VREF
current-mode [21,36-39] control. Some authors
OSC
have suggested an optimization of the small-
signal characteristics for a minimum output
impedance [22]. Fig. 18. Average current mode control.
• The control techniques that does sense the
output current transient directly or through B. Control with Slow Feedback Loop
the related change of the output voltage and This approach requires complicated
uses this signal in a fast feedback loop or feedback-loop-compensation circuitry for a stable
feed-forwards it to improve the transient converter operation at all conditions, including
response. The main examples of this group the wide range of the output capacitance that is
are hysteretic-mode [26, 29-33] and V2 -mode usually specified by the requirements [11]. The
[27,46]
control techniques. This is group control unity-gain bandwidth must be at least a few times
with a “fast” feedback loop. lower than the switching frequency, so the
dynamic characteristics of the regulator are
relatively slow. Using a small-signal model to
1-18interpret and improve the large-signal transient
response characteristics, as described in [20,22], is +
D
+
VOUT
VIN 1-D
questionable. Although these controllers are very _ _RLOAD
popular in most generic applications, their
transient characteristics are worse than the _ Driver Hyst. Comp
_
controllers having direct load-current sensing and Q
Q +
a fast load-current feedback loop.
VREF
TPS5210
C. Control with Fast Feedback Loop
The most popular implementation of the Fig. 19. Hysteretic control.
second approach is the hysteretic control and V2
mode control. The hysteretic control (or two-
state, bang-bang, ripple, free-running regulator, +
D 1-D
+
VOUT
VIN
etc.) is the simplest control approach, which has _ _ RLOAD
been used for a long time [28]. This is probably the
earliest controller or regulator. The hysteretic
Comp
controller became the solution in the new _ Driver Latch Error Amp
+
applications that require the fast load-current Q Q
_R _
_
Q +
transient response power supplies. This is a very QS
VREF
simple solution that does not require the
compensation circuitry and has the excellent
Auxilliary Logic, that sets:
dynamic characteristics. The examples of TOFF MAX, TOFF ext,
integrated circuit implementation of this TOFF norm, TON MAX
approach for modern applications are available Fig. 20. One of the implementations of V2 mode
now from a few companies, including Texas control.
Instruments (Fig. 19).
Unlike other control approaches, this The V2 mode control also has very fast
controller does not have a slow feedback loop: it transient-response characteristics, but it has
reacts on the load-current transient in the drawbacks in its original implementation
switching cycle where the transient occurs. Its (Fig. 20). This controller uses the output-voltage
transient response time depends only on delays in ripple as the ramp signal of the modulator. It is
the hysteretic comparator and the drive circuitry. assumed that the voltage ripple of the output
The high-frequency noise filter in the input of the capacitor depends mostly on the ESR, while the
comparator also adds some additional delay. part of ripple caused by the ESL and CO is
Those delays depend mostly on the level of the negligible. In this case the ripple is proportional
selected technology, and so the hysteretic control to the inductor current ripple. At the transients,
is theoretically the fastest solution. The other this voltage carries the information about the
advantage of the hysteretic controller is that its load-current change directly to the comparator,
duty cycle covers the entire range from zero to bypassing the slow main feedback loop. The V2
one. It does not have the restrictions on the mode control actually can be defined as the sort
conduction interval of the power switches that of hysteretic control having the additional error
most of the other control approaches have. This amplifier. This amplifier enables an increase of
capability is very important to decrease the the hysteresis window of the comparator without
recovery time of the output voltage after a load- degrading the accuracy of the output voltage.
current transient.
1-19On the other hand, the use of output ripple- TABLE 2. COMPARISON OF CONTROL
voltage as the ramp signal causes the stability to APPROACHES FOR HIGH SLEW-RATE TRANSIENT
depend greatly on the output capacitor parasitics. APPLICATIONS
This dependence is especially problematic when Hysteretic Voltage mode Current mode
using many high-frequency ceramic or film (ripple) control
V2 mode control
control control
capacitors in parallel as the output filter. In this 150ns - 200ns 5 - 10 µs in best case, because
case, the equivalent output capacitor is almost Reaction time
(limited only by technology) of slow feedback loop
ideal, because its parasitics are negligible and an ON/OFF time Constant OFF time in Limited by switching cycle of
practical implementation, internal oscillator in constant
output ripple has a parabolic waveform instead of duration
limitation
No
limitation that degrade transient switching frequency
a linear ramp. This ripple is also with an angle of
response implementation
Duty cycle
π/2 out of phase with the output inductor current. No limitation Yes/No Depends
limitation Yes
on part
Providing a stable operation in this situation Apparently any control allows
might be a problem. Another possible problem is implementation of the passive or active droop-
getting a reliable and predictable startup compensation techniques discussed in the
characteristic of the V2 mode controller. The transient analysis section [Fig. 9]. But the cost of
controller may require additional circuitry for the the implementation might be different. For
startup control only, as in the original example the compensation circuitry of controllers
implementation [Fig. 20]. To avoid these with slow feedback loop could be designed with
problems, the modifications of V2 mode control low load regulation for this purpose. The
superimpose the inductor-current ramp signal question is still how fast the active droop
onto the input of a comparator [46]. compensation is. Usually the droop compensation
There is another problem related to needs to complete its own transient within 1-2 µs
controllers that sense information about load to be ready for the next transient. The hysteretic
current by using output capacitor’s ESR: their controller requires an additional current sense
frequency dependence from the output filter amplifier for the active droop implementation.
parasitics and its variation related to tolerances
and variations of the capacitor characteristics. VII. EFFECT OF CONTROLLER LIMITATIONS ON
This problem could be solved by using the THE TRANSIENT RESPONSE
frequency synchronization or again, by
superimposing an additional ramp signal to avoid The previous analysis assumed that the
dependence from the output filter [29,40,41]. It is controller is ideal. The ideal controller does not
useful to mention that the compensation of have delays. It is able to maintain the on or off
controllers with the slow feedback loops also state of the respective power switches during a
depends on the output capacitor parasitic transient as long as necessary. As shown above,
variations. Table 2 shows pros and cons of the the controller parameters influence the second
discussed controllers for high-slew-rate load- peak of the transient but have no effect on the
current transient applications. first one (Fig. 5b). The real controllers do have
delays and might have some restrictions on the
duty cycle. For example, the constant on-time
controller must complete its on-cycle for the
high-side FET all the time, even when a transient
occurs.
1-20The same issue relates to the constant off-
time control, but here the off-time cycle must be ∆Vc = ∆ Qc/Co
completed. The controllers with a trigger latch VCO
working at a constant frequency usually have
restrictions on the maximum duty-cycle. Control
approaches that do not have a fast feedback loop
(which senses the load-current transient directly) IO
∆ Qc
require at least a few switching cycles until they IL
start to change the duty cycle and to respond to a
transient. This delay is caused by their low unity-
gain bandwidth of the compensation circuitry
compared to the switching frequency. Fig. 21
shows how the actual controller degrades the VG
transient waveforms at a load-current step-down.
The moment when the transient occurs is selected (a) “Ideal" controller. The moment of the transient is
to get the worst-case conditions for each kind of selected to get the worst-case condition.
controller.
tDEL
The ideal controller in Fig. 21a does not have
delays and duty-cycle restrictions. The capacitive
portion of the output voltage vCO gets the ∆ Qextra
IO
∆ QC
additional rise ∆VC because the charge ∆QC is
IL
delivered to the output capacitor CO (Fig. 1) by
the inductor LO. The delay tDEL that any real
controller has adds the extra charge ∆QEXTRA
(Fig. 21b). This additional charge increases the
second peak of the output-voltage transient VG
waveform (Fig. 4) by -∆QEXTRA /CO. The
constant on-time controller (Fig. 21c) gets the
(b) Controller with delays. The moment of the transient is
extra-charge related to the delay and to the fixed shifted to the left to get the worst-case condition.
on-time. The controller with a slow feedback
loop (Fig. 21d) has even more extra charge and tON
tDEL
related voltage-soar than the previous controllers.
This extra charge can have significant effect on Qextra
IO
the transient waveforms if the output filter has QC
relatively low output-capacitance like, for IL
instance, the ceramic capacitors in a high-
frequency regulator. Actually the extra charge
becomes more important in a low-size high-
frequency solution. There the controller
parameters could significantly affect the regulator
cost and size.
The control considerations in this section (c) Constant on-time controller with delays. The moment of
suggest that transient response makes the the transient is shifted to the left because of delays and
hysteretic controller is one of the best solutions fixed on-time.
for powering high slew-rate transient loads. The
next section is dedicated to further analysis of
this controller and some of its modifications.
1-21tDEL Fast transient-response regulators are needed
for powering devices such as modern, high slew-
∆ Qextra rate transient microprocessors, DSPs, and
IO
memory ICs. That need, and achievements in
IL analog IC design technology, have made the
hysteretic control interesting again. Modern
∆ QC hysteretic comparators have delays of only tens
of nanoseconds, with a hysteresis window around
VG 10-20 mV. This voltage is far from that of the old
Schmidt triggers with hundreds of millivolts of
(d) Controller with delays and slow feedback loop.The hysteresis in a frequency range of a few kHz. The
additional on-cycle appears because of slow feedback loop. theoretical analysis of hysteretic regulators also
Fig. 21. Impact of actual controller limitations on must now take into account component and
transient. layout parasitics that cannot be avoided at or
above a hundred kHz switching frequency and
with extremely high slew-rate transients.
VIII. MODERN HYSTERETIC (RIPPLE)
CONTROLLER AND ITS MODIFICATIONS B. Switching Frequency of Hysteretic Regulator
Switching-frequency predictability of a
A. Requirements for a Hysteretic Comparator hysteretic controller is important for a power-
There are many examples of new supply design. A simple and accurate method of
requirements and technological achievements determining the switching frequency is described
bringing new life to some old ideas and forgotten below [26]. Assume that the input and output
solutions. The hysteretic regulator is one of these voltage ripple magnitudes are relatively
examples. This regulator, based on a Schmidt negligible in comparison with the dc component.
trigger, was very popular in the 60s and early Also suppose that the time constant
70s. Unfortunately the simple scheme does not L/(RDS(on) + RL) that includes the output inductor,
always mean easy analysis and design. Later, L, the on-state resistance of the FET, RDS(on), and
more sophisticated control approaches took over the inductor resistance, RL, is high in comparison
most applications by allowing fixed-frequency to the switching period. Assume the body-diode
operation and more predictable design conduction time and switching-transition time are
procedures. Nevertheless, the hysteretic control, much shorter than the switching period. These
which by control-theory definition belongs to the assumptions are reasonable for high-efficiency
slide-mode control or a relay system, always has regulators with low output- and input-voltage
natural advantages such as fast transient- ripple. In such a case the output inductor current
response. The engine of a modern hysteretic can be modeled as the sum of the dc component
regulator is its comparator, which has a hysteresis (equal to the output current IO) and the ac linear
window. The comparator is intended to keep the ramp component, which flows through the output
output voltage and ripple within the hysteresis capacitor (Fig.22). The peak-to-peak value of the
window. In reality the ripple is always higher inductor current ∆I is equal to the following
than the hysteresis window because of the delays. equation:
Another problem is that the switching frequency
depends significantly on the power stage
characteristics and the operation conditions.
∆I =
( )
VIN – IO ⋅ R DS(on ) + R L – VOUT
⋅ D ⋅ TS (12)
L
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