Designing with the Nios II Processor and SOPC Builder Exercise Manual

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Designing with the Nios II Processor and SOPC Builder Exercise Manual Software Requirements: Quartus II 9.1 sp2 ModelSim 6.5 (Starter Edition) Nios II 9.1 sp2 Altera Megacores IP 10.1 Hardware Requirements: This lab guide is set up to allow you to use the following boards: Nios Development Kits: Stratix Stratix I 1S10, 1S10ES Stratix II Stratix II 2S60, 2S60ES, 2S60 rohs Cyclone Cyclone 1C20 Cyclone II Cyclone II 2C35, 2C35ES Cyclone III Cyclone III Starter FPGA and Nios II Embedded Evaluation Kits (NEEK) Link to the Nios II Literature: http://www.altera.com/literature/lit-nio2.jsp Use the link below to download the design files for the exercises: http://www.altera.com/customertraining/ILT/NiosII_1Day_10.1_v1.zip

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 2

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 3 Lab 1 Creating a Nios II Processor System

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 4

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 5 Objectives: Over the course of the lab today, you will create an embedded hardware system and run some software code on it.

As the lab progresses, you will continue to modify your hardware system to incorporate new features as you learn about them in class. This lab guide is set up to allow you to use any one of the following development kits, so, some written steps will pertain to one type of board; other steps to another type of board. You can tell when type of kit you are using by looking at the labeling on the FPGA package on your. Failing that, the instructor should be able to advise you. The kits fall into two main categories as shown below: Nios Development Kits: Stratix Stratix I 1S10, 1S10ES Stratix II Stratix II 2S60, 2S60ES, 2S60 rohs Cyclone Cyclone 1C20 Cyclone II Cyclone II 2C35, 2C35ES Cyclone III Cyclone III Starter FPGA and Nios II Embedded Evaluation Kits (NEEK)

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 6 Step 1: Set Up Embedded Hardware Design Project Hardware set up requirements:  USB-Blaster programming cable connected between computer and JTAG connection header or USB input on development board  Power supply connected to the board Typical Nios II Processor Development Kit 1. Navigate to the C:\altera_trn\Nios II_HW\NiosII_1Day directory on the training computer. There is a self-extracting zip file called: “NII_SOPCBuilder_ 1Day_.exe” Execute .exe and accept the default location C:\altera_trn\Nios II_HW.

Navigate into this directory and then into NiosII_1Day\. In this directory, you will find several sub-directories for each of the different types of development boards supported for this class. Inside each respective project folder is a sub-directory called niosII_lab that contains the partially completed Quartus II project that you will use as your starting point today.

2. Navigate into the appropriate project folder for your particular development kit: (Refer to the illustrated directory structure below for help or consult instructor.)

Designing with the Nios II Processor and SOPC Builder Exercise Manual

You will have to check the part on your board to confirm this. Also, please note whether your part ends with ES or not or whether it is a ROHS kit. Example Lab Directory Structure and Working Area for Stratix II 2S60ES kit Nios II Processor Development Kit 3. Then change directory into nios_II_lab located inside your particular kit’s project folder. Start the Quartus II Software by double-clicking on the project file located therein: (ie.

niosII_lab.qpf)

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 8 4. Assign device family and pinout settings to your Quartus II project by sourcing the TCL script provided in your particular working directory. From the Tools menu in Quartus II, select Tcl Scripts, and then from the Project folder choose the setup script for your particular development board (e.g. Setup_Cyclone_3C25.tcl, etc.), and click Run. This will automatically assign the relevant device settings and pin-outs to the Quartus II project for the particular FPGA development board you are using.

If you are unsure about which kit you are using, please check FPGA on development board or consult your instructor. Note: As an alternative, you may also source the Tcl script from the Tcl command prompt in Quartus II by typing “source” followed by the name of the script. For example: “source Setup_StratixII_2S60_rohs.tcl”. 5. Save your updated project settings: File > Save Project.

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 9 6. Next, you will start building your system.

It will include the following: Nios II CPU External SRAM memory controller External Flash memory controller One or more tri-state bridge components to interface with the memory components on the tri-state bus or busses on your board JTAG UART peripheral . . . PIO peripherals, configured to interface to LEDs, buttons, and a seven segment display if your board has one System clock timer High resolution timer Note: Some of these component’s settings will depend on what kit you have. Please follow the instructions for your particular board, and choose appropriately. Consult with the instructor if you are not sure which board you have.

In essence, you will be building a system that looks something like this: Outline of Hardware System

Designing with the Nios II Processor and SOPC Builder Exercise Manual

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 10 7. Start SOPC Builder from Tools => SOPC Builder... and enter the system name, niosII, when the next window pops up. You can choose VHDL or Verilog (whichever you prefer) as the implementation language. The blank SOPC builder window will open. 8. The Device Family should match the FPGA you are using (eg. Stratix II EP2S60. Ensure the External Clock frequency is set to 50 MHz for all kits.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 11 Step 2: Add Nios II Processor to System 1.

From the left hand window pane under the Processors folder select Nios II Processor and click Add. Select Nios II/s for the processor core. Select DSP Block as the Hardware Multiply option for all Stratix boards, Embedded Multipliers for all Cyclone II and Cyclone III boards, or Logic Elements for Cyclone boards.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 12 2. Click on the Caches and Memory Interfaces tab. Set the Instruction Cache size to 4 Kbytes and include one tightly coupled memory instruction master port.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 13 3. Now, click on the JTAG Debug Module tab. Select the JTAG Target Connection Download Level 3 option. This will provide us with all the debug options listed on that tab.

4. Click Finish. This will add it to the SOPC Builder system. Note: Ignore any warnings or errors you see in SOPC Builder for now.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 14 5. Rename the processor, by right clicking on it and selecting Rename. Type in cpu and hit enter. (Note: You may have to click away from the peripheral and then click back onto it again in order to rename it.) Note: It is essential for you to enter the names of all peripherals and memories EXACTLY as shown in the lab guide since these components will be referenced later on in the C–code. Also, be sure that you type each name using the correct CASE.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 15 Step 3: Add Avalon-MM Tristate Bridge (or Bridges) to System 1.

You will now add the appropriate number of Avalon-MM-to-tri-state bus-bridging peripheral/s required to let you access the various memory chips on your board. (After this you will add the appropriate memory interface controllers, themselves.) You will find the Avalon-MM Tri-State Bridge peripheral in the Bridges and Adapters section of the SOPC Builder pick-list under Memory-Mapped components. For all the boards, you will add at least one tri-state bridge. Others will require two tristate bridges. Follow the upcoming steps to see what is required of your board. 2. Add an Avalon-MM Tri-State Bridge peripheral to the design.

Select the Registered option, and click Finish.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 16 3. Then, re-name the peripheral to, ext_ram_bus. 4. For certain kits, you will have to add an additional tri-state bridge: Cyclone II 2C35 Cyclone II 2C35ES Stratix II 2S60 rohs (Note: do not add a second bridge for the non-rohs Stratix II kits) If you have one of the kits listed above, highlight the Avalon-MM Tri-State Bridge peripheral again, click Add, select the Registered option, and click Finish. Rename this second tri-state bridge peripheral ext_flash_bus.

Note: The reason that you will add a second tri-sate bridge for these particular boards is because they contain two tri-state memory buses – one for the flash and another for everything else on the PCB.

All other kits share one tri-state bus for everything, so they only require one bridge. Please consult your instructor if you are unclear.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 17 Step 4: Add Flash Memory to System 1. From the left hand window pane go to the Memories and Memory Controllers > Flash folder, highlight the Flash Memory Interface (CFI) component, and click Add. Then, choose the appropriate type of flash memory for your particular board from the Presets category (see below for choices): For all Stratix II and Cyclone II Nios Development Kits add: AMD29LV128M-123R (BYTE-Mode) preset Address width of 24 and data width of 8 For Cyclone III (NEEK) Kits add: Intel 128P30 preset Address width of 23 and data width of 16 For Cyclone III Embedded Systems Development Kit: Custom preset Address width of 25 and data width of 16 For Stratix III FPGA Development Kit: Custom preset Address width of 25 and data width of 16 For all other Stratix I and Cyclone I Development Kits add: AMD29LV065D-120R preset Address width of 23 and data width of 8 Accept the defaults, click Finish.

Then, rename the memory to ext_flash.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 18 Step 5: Add Static RAM to System Note: You will perform either Step 1 or Step 2, depending on what board you have. 1. If you have a Nios II Cyclone II, Cyclone III, or Stratix II rohs board, please skip to Step 5 (2) and add an SSRAM component. Otherwise, proceed with the instructions below. From the Memories and Memory Controller > SRAM folder in the SOPC Builder pick list, select IDT71V416 SRAM, and click Add. (You can increase the width of the picklist window to help you find the components if you want to.) Select a memory size of 1024 kB.

Click Finish, and rename the memory ext_ram. Continue to Step 5 number 3.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 19 2. If you have a Cyclone II, Cyclone III NEEK Kit, or Stratix II rohs Nios II boards, then add an SSRAM memory controller from the instead, and accept the defaults. Select Cypress CY71380C SSRAM from the Memories and Memory Controller > SRAM folder, and click Add. Choose the settings shown below. (If you are using a Cyclone III device, choose a 1 MB memory.) Otherwise, if you have a Cyclone III FPGA Development Board, then please go to the CycloneIII Host Development Kit folder and then to Memories and Memory Controllers, and select SSRAM > ssram32, and accept the defaults.

Click Finish and then rename the memory ext_ram. Choose 1 MB for Cyclone III Boards

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 20 3. Now, highlight the RAM component you just created, and move it up directly underneath the ext_ram_bus peripheral using the Move Up button located at the bottom of the work space. (Note: Doing this is not absolutely necessary but will help keep the System Contents page nice and tidy as you start adding more components and adjusting masterslave connections.) 4. Now we will establish the appropriate master slave connection settings in SOPC Builder. That is, the Nios II data master should master the “ext_ram_bus” peripheral’s avalon_slave port, and the “ext_ram_bus’s” tri-state master port should master the “ext_ram” memory, and the “ext_flash_bus,” if present, should master “ext_flash” memory.

To do this, go to the View menu in SOPC Builder, and unless it is already set for you, turn on Show Connections Column. (A check mark will appear beside your selection.) Experiment by moving your mouse over the connection panel the view to highlight either the interconnects or the master-slave connections. You can click on the circles in the interconnect to make or sever the connections. Black dots mean that the connection will be made; while white dots mean that no connection will be made (see below and see over).

move mouse to change connection view as shown Edit Mode View Mode

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 21 Your system will resemble one of the following: Connections for the Cyclone II and Stratix II rohs Nios II kits: Connections for the Stratix II DSP kits: Connections for all other Nios II kits: (including the Cyclone III kits)

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 22 Step 6: Set Connection Properties For Shared Avalon-Tristate Bridge 1. If you have a shared Avalon_tristate bridge peripheral (ie. if you have one of the kits listed below), set the ext_ram_bus tri-state bridge peripheral to share address ports between the ext_ram and the ext_flash peripherals as shown: Cyclone 1C20 Cyclone III FPGA Starter Nios II Evaluation (NEEK) Stratix 1S10 and 1S10ES Stratix II 2S60 and 2S60ES Note: Double-click on the peripheral to open it for editing.

This step is required for these kits because they have only one tri-state peripheral, so you have to share some pins through it. Then click Finish.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 23 Step 7: Add JTAG UART to System 1. From the left hand window pane find the JTAG UART from the Interface Protocols > Serial folder and click Add. Accept the defaults. (The screen should appear as shown.) Rename the peripheral to jtag_uart.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 24 Step 8: Add Another PIO to Control the LEDs 1.

Add a second PIO (Parallel I/O) peripheral with a width of 8 bits (or 4 bits for the Cyclone III boards), with output ports only set. Click Finish. Rename this peripheral led_pio. Choose width 4 for Cyclone III Boards

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 25 Step 9: Add Another PIO to Control the Buttons Labeled, “SW” 1. Select yet one more PIO (Parallel I/O) and Add it to your system. Choose width 4 bits this time, with Input ports only selected, and click Finish. Rename the peripheral button_pio.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 26 Step 10: Add Timers to System 1. Select the Interval Timer from the Microcontroller Peripherals folder and click Add.

Select the Full-Featured Preset, and click Finish. After the timer has been added to your system, rename it to sys_clk_timer.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 27 2. From the left hand window pane add another Interval Timer to the system. Change the Preset to Full-featured and the period to us. Then click Finish. (You are going to use this later when you time the speed of some of our software functions.) Rename the timer to high_res_timer.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 28 Step 11: Add System ID Peripheral to System 1.

Locate the System ID Peripheral from the Peripherals > Debug and Performance folder in the pick list, and Add it to your system. (Note: it is recommended that every SOPC Builder design that you create has a system ID peripheral!) Rename it to sysid.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 29 Step 12: Add PLL Peripheral to System 1. Now, Add the “Avalon ALTPLL” component to the project from the PLL folder. Then configure the PLL using the settings shown below. (Note: You navigate through the Wizard using the Next button.) 2. Be sure that the frequency matches that of your board (that is, 50 MHz).

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 30 You will accept most of the default PLL settings.

The settings that you have to observe and possibly change are listed in the following tables: Note: For the PLLs that require two tap outputs, C0 and C1, you must manually enable a second tap inside the PLL MegaWizard. To do this, simply click on the “Use this clock” check box on the appropriate Output Clocks page of the Megawizard. A -3.32 ns phase shift is added to the C1 output for those boards with SSRAMs. This provides an equal setup and hold on outputs to the SSRAM. Nios II Development Kits Input Freq. (MHz) Output Tap Settings C0 C1 Cyclone 1C20, Stratix 1S10, 1S10ES, Stratix II 2S60, 2S60ES 50 Mult.

Factor = 1 Div. Factor = 1 Phase Shift = 0 Stratix II 2S60 rohs, Cyclone II 2C35, 2C35ES 50 Mult. Factor = 17 Div. Factor = 10 Phase Shift = 0 Mult. Factor = 17 Div. Factor = 10 Phase Shift = -3.32 ns Cyclone III NEEK, Cyclone III FPGA Starter Kit 50 Mult. Factor = 10 Div. Factor = 5 Phase Shift = 0 Mult. Factor = 10 Div. Factor = 5 Phase Shift = -3.32 ns After you configure the PLL to match the setting shown above, select Finish. The final page of the PLL Wizard should resemble the following: (Note: there will be some minor differences depending on what language you have chosen or development kit you are using for your project.) Please consult with instructor if you are confused as to which board you are using and the settings you need to choose.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 31 Select Finish again and then Finish one more time to add the component to the SOPC Builder system; then re-name it, pll.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 32 Double click on pll_c0 in the Name column in the Clock Settings window in the top right corner of the SOPC Builder tool, and type over the text to re-name it sys_clk. (If you generated a second PLL output tap, then also re-name pll_c1 to ssram_clk.) Also change the name of incoming clock to clk.

The system Clock window should now appear as follows: Cyclone II and Stratix II rohs Nios II Development Kits: Cyclone III Development Kits All other Nios II Kits (including non-rohs Stratix II): 3. Now, click in the Clock column for the Nios II processor and all peripherals (except the pll and ssram, if your design has one) and change their driving clocks to sys_clk. Change the clock driving the ext_ram peripheral to sram_clk.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 33 Step 13: Establish IRQ Priorities 1. Assign the IRQ numbers: Go to the System menu and select Auto-Assign IRQs to establish some basic IRQ assignments. Then, take a look at the IRQ values that result. Edit them to ensure that the sys_clk_timer gets priority 0 (highest priority), that the high_clk_timer gets priority 1, and JTAG_UART gets priority 2 (lowest priority).

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 34 Step 14: Add Tightly Coupled On-Chip Memory to System 1.

Now, add the tightly coupled on-chip memory to attach to the processor. From the pick list, look inside the Memories and Memory Controllers > On-Chip folder, and select On Chip Memory (RAM or ROM) and click Add. If you have a Stratix II device on your board, set the memory block type to M4K. For other devices, leave it as the default. Keep the memory width at 32 bits, and ensure the Total Memory Size to 4 kbytes (4096 bytes).

Finally, enable Dual-Port Access. Click Finish, and rename the peripheral tightly_coupled_instruction_memory.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 35 2. Change the clock driving both tightly coupled memory ports to sys_clk, if necessary, and using the Move up button, move the peripheral up in the system contents page until it resides directly underneath the cpu. (This will make it easier to see its connections to the cpu.) 3. Ensure that the appropriate master/slave connections are made between the cpu and the Tightly Coupled Memory.

Toggling the System Interconnect Fabric Connections: Click your mouse on the appropriate dots in the tightly coupled memory’s connectivity diagram in order to toggle the connections as shown below: (Note: the connected state is solid; while the disconnected state is white.) Port S1 of the tightly_coupled_instruction_memory should be connected to the cpu’s tightly_coupled_instruction_master_0 master port, and port S2 should connect to the cpu’s data_master port. 4. You will now change the base addresses of the tightly coupled master ports (S1 and S2) so that they do not overlap any of the other peripherals in the design.

5. As a first step, go to the System menu and choose Auto Assign Base Addresses for the system. A number of error messages will disappear.

6. Next, look in the SOPC Builder message window (toward the top), and find the cpu warning message concerning the tightly_coupled_instruction memory. Double-click in the Base address box and edit the values to 0x02402000. Then lock the values (right-click > Lock Base Address or click the Lock icon). Step 15: Take a Look at Your System

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 36 1. To again ensure that all base addresses are valid, go to the system menu or right click on any one of the base addresses in the table and select Auto-Assign Base Addresses.

2. Your SOPC Builder System Contents page should now appear similar to the following: For the Nios II Cyclone II and Stratix II rohs kits: Driving clocks excluded from diagram but visible in SOPC Builder

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 37 For the Cyclone III NEEK kit: For the Cyclone III Embedded Development kit:

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 38 For all other Nios II kits:

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 39 Step 16: Establish Reset and Exception Handler Locations 1.

Now, you will go back and set the exception and reset addresses for the Nios II processor. Double-click on the “cpu” peripheral, and look at the bottom of the Core configuration page: This is where you can establish the reset and exception addresses of the CPU. Select: ext_flash for the Reset Address and ext_ram (or ext_ssram) for the Exception Address Click Finish.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 40 2. In the System Contents tab Warning and Message area, check to see if you have any remaining memory address violations. If you do, then go to the System menu one more time, and select Auto-Assign Base Addresses. This should get rid of them. 3. In SOPC Builder, click Next to go to the System Generation tab, and uncheck the Simulation checkbox if it is checked. 4. Save your SOPC Builder system (File > Save). 5. Next, click Generate. SOPC Builder will now create the parameterized SOPC system.

Note: If you happen to receive a warning message in SOPC Builder that prevents you from generating the system, check to make sure that all the peripherals are connected to sys_clk. For example, you might encounter a message like: the cpu/tightly_coupled_instruction_master_0 may connect to 1 slave only If setting sys_clk does not solve your problem, try closing SOPC Builder and then reopen it again in order to register the change you just made.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 41 6. After SOPC Builder has finished generating your embedded sub-system, open the niosII_lab.bdf schematic in Quartus II using File->Open or by double-clicking on it in the Project Navigator: 7. Zoom in or out in the schematic, as needed, using the magnifying glass utility. The schematic editor should resemble the following: (Note: There will be some variation in the schematic depending on what kit you have.)

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 42 8.

Then switch back to the Selection Tool arrow, and double-click anywhere on the schematic editor to open the Symbol viewer. Once in Symbol viewer, Open the Project folder, and click on the niosII symbol. 9. Add the niosII component to your Quartus II project by pressing OK; then drop the symbol into your schematic so that its pins line up exactly with the pin placements as shown below. These pinouts have already been done for you.

Note: If the pins do not all line up exactly, then you will need to go back to SOPC Builder and re-check your work.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 43 The hook-up should resemble the following: Diagram above shows the Cyclone III system instantiated into the top level block diagram. 10. Check to ensure that the niosII.qip file has been added to the project (Project > Add/Remove Files in Project) before you select OK. 11. Save the schematic (File > Save). 12.

Save the Quartus II project (File > Save Project). 13. Start compilation in Quartus II by selecting Start Compilation from the Processing menu. If compilation should fail for the Cyclone III board, be sure to set all “Dual Purpose pins” as regular IO: (Assignments > Device > Device and Pin Options > Dual Purpose Pins). Then try again.

14. When compilation completes, select OK. You may see some timing violations in your project. These can be fixed at the expense of compilation time. For this class the timing violations will not affect the operation of the labs. You will continue from this point during the next lab. END OF LAB 1

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 44

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 45 Lab 2 Software Flow

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 46

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 47 1. You will now download the Nios II FPGA design created in the previous lab to the Nios development board. Within Quartus II, go to the Tools menu, and select the Programmer. (If the .sof file for your project does not populate the File field then click on the Add File button . Then select file niosII_lab.sof and click Open.) 2.

Tick the Program/Configure checkbox for that .sof file, and then click the Start Programming icon . Close the programmer after the device has been programmed. If the Start Programming button is not enabled, make sure your Hardware Setup field (at the top of the Programmer window) reads USB-Blaster or Byteblaster. If not, click on the Hardware Setup button and choose USB-Blaster or Byteblaster from the drop-down menu, and click Close.

3. Launch the Nios II Software Build Tools for Eclipse from SOPC Builder (see Nios II menu > Nios II Software Build Tools for Eclipse). When the Workspace Launcher appears, set the workspace to: C:\altera_trn\NiosII_HW\NiosII_2Day\Day1\\NiosII_lab, and press OK. 4. Create a new software project by selecting File -> New-> Nios II Application and BSP from Template. 5. In the Target hardware information box browse to the .sopcinfo file created from SOPC Builder. 6. In the Application project box type niosII_training_project as the name of the project. Select the Blank Project template as the Project Template.

The New Project window should now resemble the following:

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 48 7. Press Finish. 8. You have now created two new projects in the Nios II Eclipse Platform - a Nios II Application project and a BSP project. However, the Nios II Application project is blank and you need to add some source code to it. To add the file, simple.c, to the project, first expand the niosII_training_project folder in the Nios II Eclipse Platform. Then, using Windows Explorer, browse to ~NiosII_2Day\\nios_II_lab\software, and find simple.c.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 49 Drag simple.c into the niosII_training_project folder in the Nios II Eclipse Platform as illustrated: 9.

Now, highlight the niosII_training_project_bsp folder, right-click, and select Properties. Then, choose Nios II BSP Properties from the left hand side of the Properties window. drag

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 50 10. From the Nios II BSP Properties window click the BSP Editor button. 11. Under the Settings Common folder ensure that the stdout, stderr and stdin devices are set to jtag_uart and that the sys_clk_timer is set to sys_clk_timer. 12. Click on the Linker Script Tab at the top of the BSP Editor. 13. Ensure Linker Sections are assigned to ext_ssram for Cyclone II, Cyclone III and Stratix II rohs boards. For all other boards these sections should be assigned to ext_ram.

14. Click Generate and Exit to close the BSP Editor. Then press OK to close the BSP project properties.

15. Compile the program by highlighting the niosII_training_project folder in the Project Explorer window; then right-click and select Build Project.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 51 Note: You can choose to run this command in the background when prompted. This will free up the tool, letting you continue to use it for other tasks; whereas, running it in the foreground causes you wait for it to complete.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 52 16.

After the compiler has finished, download and run the program on the development board: Highlight the niosII_training_project folder then right-click and select Run As-> Nios II Hardware. (see next) Note 1: If Run terminates before the code downloads to your board, and you get a message pertaining to the JTAG download cable. then select Run > Run... and from the Target Connection tab choose the appropriate download cable that you are using and then press Apply and Run (or see instructor). Note 2: The Nios II Eclipse Platform will actually Build the project automatically for you if you just click Run As -> ...Nios II Hardware without you having to explicitly go through the Build step.

You can enable or disable this option in the Window > Preferences.

If the Run Configuration window comes up verify there are no errors with the build and press Run. This will download the program to the development board. You should observe that the console window in the Nios II Eclipse Platform displays the printf statement (“Simple”) from the simple.c file.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 53 Press any of the four buttons on the board (located under the LEDs) to shift the LED pattern to the right. (NOTE: on the NEEK board the LEDs will shift to the left.) 0, 1, 2, 3 17.

Now, let’s run the debugger on this design and step through some code. Start by opening “simple.c” and then running the debugger by highlighting the niosII_training_project software project folder, then right-clicking on it, and selecting Debug As-> ...Nios II Hardware.

Choose, Yes to “Do you want to open this perspective now?” when prompted. LEDs shift to the right

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 54 18. Turn on line numbers in the C file editor. To do this, go to the Window menu, and select Preferences. Open the General folder followed by the Editors sub-folder. Select Text Editor; then check Show line numbers. Press OK. 19. Set breakpoints on the first “if” statement (line 40) and the second “while” statement (line 55). To set a breakpoint, simply place the cursor on the line number or grey area next to it, and double-click.

A circle should now appear next to the line number indicating that a breakpoint is set.

20. Click on the resume button . 21. Now, go to the Variables window, and view the contents of the buttons variable. Notice that the button value has been read (The “none-pressed” value is 15). Click resume again. Since the “if” expression is false (no buttons are pressed) the statements within the curly braces are not executed, and thus you will not break on the “while” statement. Instead it will break on the “if” statement. 22. Hold down the right-most button on the board and click resume. Notice that a new value is stored in the buttons variable. (The value of led indicates its position on the board.) 23.

Continue to hold down right-most button and click resume again. Since a button was pressed when you advanced the debugger this time, the breakpoint on the “if” statement is now caught, the “if” condition is true. Notice that the illuminated LED has also changed position and the led variable has changed.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 55 24. Release the button, and click on the resume button until the program returns to the “if” statement. 25. Within the Variables window, select and highlight the value of buttons. Then, manually change it to 0xe, and hit Enter. Click resume. Notice that the “if” statement is executed again due to the change you just made. Editing the variable values in this way is useful because it gives you a way to emulate external hardware events or other conditions that may otherwise be difficult to replicate! 26.

Now terminate and remove the program. Go to the Debug sub-menu menu; rightclick on the software project thread, and select Terminate and Remove.

Optional Section: Use the System Console to exercise your SOPC Builder System Run System Console script from Nios II Command Shell 1. Open a Nios II Command Shell from the Windows Start > Programs menu: 2. Change into the lab working directory by typing the following at the Nios II Command prompt: cd For Example: cd C:/altera_trn/NiosII_HW/NiosII_2day/Day1/NiosII_CIII_3C25/niosII_lab Note: to speed up the process of typing the path, you can drag the path from a Windows Explorer window directly into the Command Shell, provided you enclose it in quotes. 3. Run the “blink_LEDs.tcl” script (located in your project directory) on the command line.

Eg. system-console -script=blink_LEDs.tcl 0x9000 (Be sure to use the base address of the led_pio peripheral in your own SOPC system.) 4. Watch the LEDs on the board blink back and forth.

5. You are now controlling the board without any software intervention! Please open the Console for the version of Quartus II that you are using

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 57 For your information, the system-console script is listed below: - - # Runs an led "lightshow" for the specified number of times # # Sample Usage: system-console -script=blink_LEDs.tcl 0x9000 - - proc run_led_lightshow { master addr count } { # # Set the values to write to the LED pio: set led_vals {0 1} # # Write the values to LED's address: open_service master $master while { $count>0 } { foreach val $led_vals { master_write_8 $master $addr $val # # Insert some delay...

for { set set led_base_addr [lindex $argv 0] } else { # If no command line arguments are provided, # set default value for base_addr set led_base_addr 0x0 } processor_stop $jtag_master puts "" # Run LED light show (5 times): run_led_lightshow $jtag_master $led_base_addr 5 puts "" } END OF LAB 2

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 58

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 59 Lab 3 Custom Peripherals

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 60

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 61 In this lab you are going to add a user peripheral to your design and run some software to test it.

1. Return to SOPC Builder. 2. In the System Contents tab, uncheck the “Use” box next to the led_pio peripheral. You will instead drive the LEDs from a PWM peripheral that you are about to import. 3. Open the Component Editor from the File menu by selecting New component. Then go to the HDL Files tab or by double-clicking the New Component icon in the Component Library.

4. Go to the HDL file tab in the Component Editor. Click Add... and browse for “avalon_pwm.v” or “avalon_pwm.vhd”, depending on which language you have chosen. Click Open. SOPC Builder will run the Quartus II analyzer to verify whether there are any syntax errors in the code. 5. Once it completes, make sure that the Top Level Module points to avalon_pwm. 6. Go to the Signals tab and verify that the ports from the avalon_pwm module have populated in the Name column. 7. Next, you need to stitch the peripheral into the System Interconnect Fabric by mapping its signals as shown below. Choose interface type “clock_reset” for signals clk and clr_n and choose “new Conduit” for pwm_out.

Make sure the signals are mapped to the Signal Types shown.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 62 8. Take a look at interface type “avalon_slave_0”. Set the Associated Clock and Reset as shown. Set the Read and Write timing parameters to 0.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 63 9. Finally, go to the Library Info tab, and observe the default settings. Set the component Group to User Logic. (You will have to type this because it is not a default folder in the pick-list).

This tells you where to look for the component in the pick list when you need to incorporate it into an SOPC Builder system. Also, change the display name to avalon_pwm. 10. Click Finish and then Yes, Save when the next dialog box appears. 11. Look for the User Logic folder in the SOPC Builder pick list. If you are unable to see the User Logic folder, then go to the File menu, and select Refresh Component List.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 64 12. Locate the avalon_pwm component you have just created inside the User Logic folder. Add it to your system. 13. Rename the peripheral to my_pwm and change its clock to sys_clk, if necessary. 14. Go to the System menu and Auto-Assign Base Addresses to clear up base address conflicts if any appear. 15. Click on the System Generation tab; uncheck the Simulation box. 16. Save your system and then re-Generate.

17. Once the system has re-generated go to the schematic editor in Quartus II; select and then right-click on the niosII symbol; and choose Update Symbol or Block.

(Observe how your changes have affected the ports on the symbol.) 18. Save the updated schematic. File => Save, and Compile the new design by clicking . Click OK when compilation has completed successfully. (Note: Quartus II may ask you to close the Block Editor – this means close SOPC Builder.) 19. Open the Quartus II Programmer by clicking on or by going to the Tools menu. 20. Check the Program / Configure box for niosII_lab.sof, and press Start to download the new design to the development board.

21. Go back to the Nios II Eclipse Platform, and create a new software project. (File -> New->Nios II Application and BSP from Template). 22. Select the Blank Project template from the Project Template panel on the left hand side of the window, and name the application niosII_pwm_project. Then specify your sopcinfo file, niosII.sopcinfo, as the SOPC Information File and click Finish.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 65 23. Use Windows Explorer to drag pwm.c and the accompanying header file, altera_avalon_pwm_regs.h, to the niosII_pwm_project folder in the Nios II Eclipse Platform.

24. Right-click on niosII_pwm_project, and select Build Project and then Run in Background. 25. After build completes right-click and select Run As-> Nios II Hardware. Note: If Run terminates before the code downloads to your board and you get a message that you have “more than one JTAG cable available”, etc. then select Run > Run... Then, from the Target Connection tab, choose your download cable, press Apply, and Run.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 66 26. The message “Nios II PWM Lab” should now be seen in the Console Window in the Nios II Eclipse Platform followed by the question: “Please enter a LED intensity value between 1 and 4 (0 to exit)”. 27. Place your mouse underneath the text and then click to set the cursor, and adjust the LED brightness by typing 1, 2, 3 or 4 followed by a carriage return, etc. 28. If you press 0 on your keyboard, it will terminate the program loop. END OF LAB 3

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 67 Lab 4 Custom Instructions

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 68

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 69 In this lab you will examine how you can boost the performance of a Nios II system without having to increase the clock frequency by incorporating custom instructions and/or the DMA controller peripheral. First, you will look at the performance of a Nios II design before and after you add a custom hardware instruction to the system.

You will implement a CRC instruction which is an algorithm used to detect whether or not data has been corrupted during transmission. It detects a higher percentage of errors than a simple checksum. The CRC calculation consists of an iterative algorithm involving XORs and shifts which execute much faster in hardware than in software. Many algorithms besides the CRC algorithm can achieve similar improvements by implementing the algorithm in hardware. CRC is just one example.

After this, you will examine how you can off-load the CPU and prevent it from getting bogged down by memory accesses which could otherwise be performed by a DMA controller. 1. Return to SOPC Builder in order to edit the system. (You may have to re-open this from Quartus II if you closed it in a previous step.) 2. Double-click on the cpu module that you have already instantiated in the SOPC Builder System Contents page to re-open the cpu dialog box. 3. Then, select the Custom Instructions tab, and press Import...

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 70 4.

The Component Editor will open. Go to the HDL files tab, and choose Add. Look for the hardware file “crc_ci.v” for the crc custom instruction, and click Open. 5. Enter crc_ci for the Top Level Module if it is not already set. 6. On the Signals tab, ensure that the interface types for all signals are set to nios_custom_instruction_slave_0 and the Signal Type is set as follows: (You may have to change the clk and reset signals to match.) 7. Now, go to the Interfaces tab, press Remove Interfaces with No Signals (if required), and then find the nios_custom_instruction_slave_0 interface that you just created and define its properties: 8.

Ensure that the “Type” is set to “Custom Instruction Slave”. 9. Keep the rest of the defaults.

10. Select Finish and then Yes, Save.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 71 11. The crc_ci custom instruction should now be located in the library list. (If it does not appear, press import again and then close it, and it should now appear.) 12. Add it to your processor, and change its name to crc, by highlighting it as shown below. 13. Then press enter, and select Finish. 14. Now, click on the System Generation tab in SOPC Builder, and make sure the Simulation check box is unchecked.

15. From the SOPC Builder File menu, Save the system (or type Ctrl-S). 16. Re-Generate the SOPC Builder system. 17. After system generation completes, you would normally update and save the SOPC Builder symbol in Quartus II by right-clicking on it in the schematic and selecting Update Symbol or Block. However, since the Custom Instruction will add additional ports to the system block - for clock and reset – you are not going to do that this time. If you do, you will have to manually cut and paste the signals to re-assign them to the appropriate ports.

18. Instead, simply Save and then recompile the design by clicking the compile icon.

Once compilation completes, click OK.

Exercise Manual Designing with the Nios II Processor & SOPC Builder Copyright © 2010 Altera Corporation A-MNL-NIIHW-EX-10-1-v2 72 Re-Program the FPGA 1. Open the Quartus II programmer. Click on . 2. Tick the Program / Configure box. Click Start to download the design to the development board. Create Software Project to Test CRC Custom Instruction Against Software Execution 1. In the Nios II Eclipse Platform, create a new project using a Blank Project template (File > New > Nios II Application and BSP from Template); name the project crc_project. Then specify your sopcinfo file, niosII.sopcinfo, as the SOPC Information File.

Then click Finish.

2. From Windows Explorer, drag the crc.c file (which is located in the software directory in your design database) into the crc_project software application project folder in the Nios II Eclipse Platform. 3. If you are using a Cyclone III kit, also add the altera_avalon_pwm_regs.h file to the project. (Since there is no seven segment display on these kits, you will flash the LEDs to signify that the test has completed.) 4. Highlight and right-click on crc_project_bsp, and select Properties. On the Nios II BSP Properties page Change the Optimization level to Level 3.

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