Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness - MDPI
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electronics
Article
Area-Efficient Embedded Resistor-Triggered SCR
with High ESD Robustness
Fei Hou , Feibo Du, Kai Yang, Jizhi Liu and Zhiwei Liu *
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and
Technology of China, Chengdu 610054, China; houfei412@hotmail.com (F.H.); dufeibo@outlook.com (F.D.);
yk18215518224@outlook.com (K.Y.); jzhliu@uestc.edu.cn (J.L.)
* Correspondence: ziv_liu@hotmail.com
Received: 21 March 2019; Accepted: 17 April 2019; Published: 18 April 2019
Abstract: The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was
effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW)
is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the
layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is
proposed in this paper. As verified in a 0.3-µm CMOS process, the proposed ERTSCR exhibits lower
triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path.
Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM
ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain
the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully
utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a
larger top metal width.
Keywords: electrostatic discharge (ESD); silicon-controlled rectifier (SCR); deep n-well resistor;
trigger voltage
1. Introduction
The silicon-controlled rectifier (SCR) has been widely used in electrostatic discharge (ESD)
protection for a long time due to its significantly high robustness and area efficiency [1]. However,
the SCR device still has a higher trigger voltage, which is generally greater than the gate-oxide
breakdown voltage of the protected device [2]. Thus, some modified SCR devices and trigger-assist
SCR devices have been invented to reduce the trigger voltage of SCR, such as the modified lateral SCR
(MLSCR) [3], the low-voltage triggering SCR (LVTSCR) [4,5], the GGNMOS-triggered SCR [6] and the
diode chain triggering SCR (DTSCR) [7]. Furthermore, the direct-connected SCR (DCSCR) has been
proposed to significantly reduce the trigger voltage to a level that is as low as twice of one diode’s
turn-on voltage [8–13].
The cross-sectional view and equivalent circuit diagram of the conventional DCSCR are shown in
Figure 1a,b. As shown in Figure 1a, the main SCR conduction path of DCSCR (illustrated by a red
arrow) is triggered by two direct-connected diodes D1 (P+/NWELL diode) and D2 (PWELL/N+ diode),
which are located in the adjacent NWELL and PWELL, respectively (illustrated by a blue arrow named
as diode chain path). These two diodes are connected by anode gate (N+ in NWELL) and cathode gate
(P+ in PWELL), which are connected together by a metal connection. Unlike the PWELL grounded in
the conventional lateral SCR structure, the PWELL in DCSCR is not grounded and thus, a deep NWELL
(DNW) is required to isolate PWELL from the P-type substrate (PSUB) [9]. Generally, the minimum
extension (L1) of a DNW region beyond a PWELL region is several micrometers according to the layout
design rule, which will result in the DCSCR consuming more silicon area compared to the conventional
Electronics 2019, 8, 445; doi:10.3390/electronics8040445 www.mdpi.com/journal/electronics
Electronics 2019,8,8,445
Electronics2019, 445 22 of
of8 8
silicon area compared to the conventional SCR. To optimize the layout area of DCSCR, an embedded
SCR. To optimize the layout area of DCSCR, an embedded resistor-triggered silicon-controlled rectifier
resistor-triggered silicon-controlled rectifier (ERTSCR) is presented in this work. Compared to the
(ERTSCR) is presented in this work. Compared to the conventional DCSCR with a figure of merit
conventional DCSCR
Electronics 2019, 8, 445 with a figure of merit (FOM) of 3.30 mA/μm2, the FOM of proposed ERTSCR
2 of 8 is
(FOM) of 3.302 mA/µm , the FOM of proposed ERTSCR is 3.66 mA/µm2 , which is higher by 10.9%
2
3.66 mA/μm , which is higher by 10.9% compared to that of the conventional DCSCR. Additionally,
compared
silicontoarea
thatcompared
of the conventional
to the DCSCR.
conventional Additionally,
SCR. To a
optimizethe proposed
themetal areaERTSCR
layoutconnection hasanmore
of DCSCR, robustness
embedded
the proposed ERTSCR has more robustness and uniform against the huge ESD
and aresistor-triggered
uniform metal connection against the huge ESD current.
silicon-controlled rectifier (ERTSCR) is presented in this work. Compared to the
current.
conventional DCSCR with a figure of merit (FOM) of 3.30 mA/μm2, the FOM of proposed ERTSCR is
3.66 mA/μm2, which is higher by 10.9% compared to that of the conventional DCSCR. Additionally,
the proposed ERTSCR has more robustness and a uniform metal connection against the huge ESD
current.
(a) (b)
Figure1.1.(a)
Figure (a)Cross-sectional
Cross-sectionalview
viewofofconventional
conventionalDCSCR.
DCSCR.The Thetrigger
triggerpath
pathisisillustrated
illustratedby
byaablue
blue
arrow that is called the diode (a)
chain path; (b) Equivalent circuit diagram of (b)
conventional
arrow that is called the diode chain path; (b) Equivalent circuit diagram of conventional DCSCR. DCSCR.
Figure 1. (a) Cross-sectional view of conventional DCSCR. The trigger path is illustrated by a blue
2.2.Proposed
Proposed ESD Device Structure and Simulation
arrowESD Device
that is Structure
called the and
diode chain Simulation
path; (b) Equivalent circuit diagram of conventional DCSCR.
InInthe
theconventional
conventionalDCSCR, DCSCR,the theDNWDNWcannotcannotbe befully
fullyutilized
utilizedalthough
althoughitithas hasaasufficient
sufficientwidthwidth
2. Proposed ESD Device Structure and Simulation
ofofL1.
L1. Actually, the DNW has the same doping type as NWELL and thus, it can be regardedasasan
Actually, the DNW has the same doping type as NWELL and thus, it can be regarded an
embedded In deep
the conventional DCSCR, the),DNW cannot be fully
theutilized
surfacealthough it has a sufficient width
embedded deepwell wellresistor
resistor (R(R which conduct of DNW
DNW), which conduct the surface of DNW region and the NWELL
DNW region and the NWELL
region.of L1. Actually,the the DNW has the same doping type as NWELL and thus, region
it can be regarded as an
region.Therefore,
Therefore, theN+ N+active
activeregionregionof ofthe
theanode
anodegategatein inthe
theNWELL
NWELL regioncan canbebemoved
movedtotothe the
surfaceembedded
ofofDNW deep well
region, resistor
which (R
will DNW), which conduct the surface of DNW region and the NWELL
not affect the turning on ofofD1 and D2. By making use ofofthe
surface DNW region, which will not affect the turning on D1
region. Therefore, the N+ active region of the anode gate in the NWELL region can be moved to the
and D2. By making use the
conductive
conductive DNW,
DNW, an
an area-efficient
area-efficient ERTSCR
ERTSCR isisproposed
proposed ininthis
this paper.
paper. TheThe cross-sectional
cross-sectional view
view and
and
surface of DNW region, which will not affect the turning on of D1 and D2. By making use of the
equivalent
equivalent circuit
circuit diagram
diagram of
of proposed
proposed ERTSCR
ERTSCR are
are shown
shown in Figure 2a,b.and It can becan
observed that
conductive DNW, an area-efficient ERTSCR is proposed in thisinpaper.
Figures The2a 2b. It
cross-sectional viewbe and
observed
the anode
thatequivalentgate in
the anodecircuit ERTSCR
gate in ERTSCR
diagram is moved from
is movedERTSCR
of proposed NWELL
from NWELL to DNW
are shown to DNW and is connected
and2a
in Figures is and
connected to the
2b. It can cathode
tobe
theobserved gate
cathode gate in
adjacent
in adjacent PWELL
that the PWELL
anode by
gatea metal
by inaERTSCR
metal connection.
is moved Compared
connection. Compared
from NWELL with
with
to the
DNW theDCSCR
DCSCR
and structure
structure
is connected to shown
shown
the ininFigure
cathode gate 1a,
Figure 1a,
the lateral
in dimension
adjacent PWELL ofbyNWELL
a metal in ERTSCR
connection. will decrease
Compared with due
the
the lateral dimension of NWELL in ERTSCR will decrease due to the removal of anode gate, to
DCSCRthe removal
structure of anode
shown ingate,
Figure while the
1a, while
lateral dimension
the
the laterallateral
dimension of DNW
dimension of of isNWELL
DNW unchanged.
is unchanged. Correspondingly,
in ERTSCR will decrease due
Correspondingly, the layout
tothe area ofarea
the layout
removal ERTSCR
of anode is smaller
gate,
of ERTSCR while than
is smaller
that theDCSCR,
of lateral dimension
which of DNW
leads to a is unchanged.
smaller layout Correspondingly,
area cost. From the layout
above, the area
use ofofERTSCR
R is smaller
can reduce the
than that of DCSCR, which leads to a smaller layout area cost. From above, the use of RDNW can reduce DNW
device than that ofarea.
layout DCSCR, In which
the leads to a R
meantime, smallerplays
layoutan area cost. Fromrole
important above,in the
the use of RDNW
trigger can reduce
path. Compared
the device layout area. In the meantime, DNWRDNW plays an important role in the trigger path. Compared
with the devicethe layout area. In the meantime, RDNWhas plays an important role series
in the triggerD1 path. Compared
withDCSCR,
DCSCR, the diode
diode chain
chain path
path ininERTSCR
ERTSCR hasone
onemore
moreRDNW RDNWin in serieswith
with DCSCR, the diode chain path in ERTSCR has one more RDNW in series with D1 and D2. However,
with D1and andD2.D2. However,
However,
RRDNW is a conductor in trigger path and thus, the triggering of ERTSCR
DNW is a conductor in trigger path and thus, the triggering of ERTSCR is still mainly determined by
is still mainly determined by
RDNW is a conductor in trigger path and thus, the triggering of ERTSCR is still mainly determined by
the turning on of two embedded diodes D1 and D2,
the turning on of two embedded diodes D1 and D2, which is similar to DCSCR. which is similar to DCSCR.
the turning on of two embedded diodes D1 and D2, which is similar to DCSCR.
(a) (b)
Figure (a) of proposed ERTSCR. The DNW acts as an embedded(b)
Figure 2. (a)2.Cross-sectional
(a) Cross-sectional view
view of proposed ERTSCR. The DNW acts as an embedded wellwell
resistor
resistor
RDNW
RFigurein in the
the trigger
trigger path;(b)
path; (b)Equivalent
Equivalent circuit
circuit diagram
diagram ofof
proposed ERTSCR.
proposed ERTSCR.
DNW 2. (a) Cross-sectional view of proposed ERTSCR. The DNW acts as an embedded well resistor
RDNW in the trigger path; (b) Equivalent circuit diagram of proposed ERTSCR.
Electronics 2019, 8, 445 3 of 8
In order to further explore the physics mechanisms of the DCSCR and proposed ERTSCR, a two
Electronics 2019, 8, 445 3 of 8
dimension (2D) Technology Computer-Aided Design (TCAD) simulation was carried out using the
Sentaurus tool, where the substrate of the device was regarded as the only heat sink and the ambient
In order to further explore the physics mechanisms of the DCSCR and proposed ERTSCR, a two
temperature was set at 300 K. The current density distributions in the triggering procedures of the
dimension (2D) Technology Computer-Aided Design (TCAD) simulation was carried out using the
DCSCR Sentaurus
and proposed tool, whereERTSCR are shown
the substrate of the in Figures
device 3 and 4.asWhen
was regarded the onlythe ESD
heat sinkpulse
and thethat is applied to
ambient
the anode of both DCSCR
temperature was set at and
300 ERTSCR is more
K. The current than
density two timesinone
distributions diode’s turn-on
the triggering proceduresvoltage,
of the D1 and
D2 turn on and the trigger current flows through the diode chain path of each device (astoshown in
DCSCR and proposed ERTSCR are shown in Figures 3 and 4. When the ESD pulse that is applied
Figures the
3a anode
and 4a). of both
AsDCSCR andthe
a result, ERTSCR is morelateral
parasitic than two
NPNtimestransistor
one diode’sand
turn-on
PNPvoltage, D1 and turn
transistor D2 on (as
turn on and the trigger current flows through the diode chain path of each device (as shown in Figures
shown in Figures 3b and 4b). As the current continues to increase, the current gain of the parasitic
3a and 4a). As a result, the parasitic lateral NPN transistor and PNP transistor turn on (as shown in
NPN transistor
Figures 3b(β NPN) and the current gain of the PNP transistor (βPNP) will increase. Consequently,
and 4b). As the current continues to increase, the current gain of the parasitic NPN transistor
this gives rise) to
(βNPN andthetheregeneration between
current gain of the the two(βparasitic
PNP transistor NPN and PNP transistors and thus, SCR
PNP ) will increase. Consequently, this gives rise to
paths arethe
triggered
regeneration (asbetween
shownthe in Figure 3c and
two parasitic NPN 4c).
andFinally, the SCRand
PNP transistors paths
thus,of both
SCR DCSCR
paths and ERTSCR
are triggered
(as shown in Figures 3c and 4c). Finally, the SCR paths of both DCSCR
discharge more current than the parallel diode chain paths due to the smaller turn-on resistanceand ERTSCR discharge more (as
current than the parallel diode chain paths due to the smaller turn-on resistance (as shown in Figures
shown in Figures 3d and 4d). Compared to the current density distributions in DCSCR, the current
3d and 4d). Compared to the current density distributions in DCSCR, the current density distributions
density distributions
in ERTSCR indicate in ERTSCR
that the DNWindicate
acts asthat the DNW
an electrical acts asbetween
connection an electrical
D1 and connection
D2 to conductbetween
the D1
and D2 to conduct
trigger current.the trigger current.
Figure 3.Figure
Total current
3. Total density
current densitydistributions at different
distributions at different currentcurrent
levels in levels
DCSCR.in (a) DCSCR.
The trigger(a) The trigger
current
flows along diode chain path; (b) the parasitic NPN and PNP transistors turn
current flows along diode chain path; (b) the parasitic NPN and PNP transistors turn on; (c) on; (c) the SCR path is the SCR
triggered; and (d) the ESD current distribution after holding point.
path is triggered; and (d) the ESD current distribution after holding point.
Electronics 2019, 8, 445 4 of 8
Electronics 2019, 8, 445 4 of 8
Figure 4.Figure
Total4.current density
Total current distributions
density distributionsatat different current
different current levels
levels in proposed
in proposed ERTSCR. ERTSCR.
(a) The (a) The
trigger current flows along diode chain path; (b) the parasitic NPN and PNP
trigger current flows along diode chain path; (b) the parasitic NPN and PNP transistors transistors turn on; (c) turn
the on; (c)
SCR path is triggered; and (d) the ESD current distribution after holding point.
the SCR path is triggered; and (d) the ESD current distribution after holding point.
3. Layout Design of Proposed ERTSCR
3. Layout Design of Proposed
The proposed ERTSCRERTSCR
has been fabricated together with a conventional DCSCR in a 0.3-µm
CMOS process. Figure 5a,b illustrate the layout top views of the conventional DCSCR and proposed
The proposed ERTSCR has been fabricated together with a conventional DCSCR in a 0.3-μm
ERTSCR with the same device width of 75 µm. In accordance with the design rule of this 0.3-µm CMOS
CMOS process. Figures
process, the 5a and
conventional 5b illustrate
DCSCR has a device thelength
layout topµm,
of 21.4 views
whileof thethe conventional
proposed ERTSCR has DCSCR
a and
proposed ERTSCR
device length with
of 19.3the
µm,same device
with an width of
area reduction 75 μm. In accordance
of approximately 10% compared with the
with thedesign
DCSCRrule
as of this
0.3-μm CMOS process,
illustrated the conventional
by the yellow DCSCR
rectangle in Figure 5a. has a device length of 21.4 μm, while the proposed
ERTSCR hasFor SCR type
a device devices
length with μm,
of 19.3 a smaller
withturn-on
an arearesistance
reduction andofhighest ESD current
approximately conduction
10% compared with
capability per unit, the robustness of metal connection from the PADs to the anode and cathode of
the DCSCR as illustrated by the yellow rectangle in Figure 5a.
SCR device will be critical in the development of an optimized ESD discharging structure [14–16].
ForRegarding
SCR type thedevices
conventionalwithDCSCR
a smaller turn-on
structure, as shownresistance
in Figureand highest
5a, the ESD current
metal connections conduction
of PADs
capability
andper unit, the robustness
anode/cathode have been split of into
metal connection
six metal fingers by from the PADs
the metal to the
connections anodetheand
between cathode of
anode
SCR device
gate will be critical
and cathode in theboth
gate since development
metal connectionsof anusedoptimized ESD discharging
metal2. According structure [14–16].
to the measurements,
the width of each metal finger is only 5.1 µm and thus, the total valid
Regarding the conventional DCSCR structure, as shown in Figure 5a, the metal connections metal connection widths of PADs of PADs
to anode/cathode will be reduced from 75 µm to 30.6 µm. However, in the proposed ERTSCR structure
and anode/cathode have been split into six metal fingers by the metal connections between the anode
as shown in Figure 5b, the metal connections between PADs and anode/cathode and the ones between
gate andthecathode gateand
anode gate since both
cathode metal
gate connections
can use different metalused metal2.
layers, According
such as metal2 and to the measurements,
metal1, respectively. the
width ofThus,
eachthemetal
metalfinger is only
connections 5.1 μm
of PADs and thus, the
to anode/cathode in total
ERTSCR valid
willmetal
spreadconnection widths
all over the full device of PADs
to anode/cathode willtotal
width and their bevalid
reduced
widthsfrom
will be75 μminto
75 µm this30.6 μm.TheHowever,
design. larger metalinconnection
the proposed
width inERTSCR
structure as shown in Figure 5b, the metal connections between PADs and anode/cathode and the
ones between the anode gate and cathode gate can use different metal layers, such as metal2 and
metal1, respectively. Thus, the metal connections of PADs to anode/cathode in ERTSCR will spread
all over the full device width and their total valid widths will be 75 μm in this design. The larger
Electronics 2019, 8, 445 5 of 8
ERTSCR2019,
Electronics results in
a smaller metal resistance of device connection and effectively troubleshoots
8, 445 the8
5 of
metal connection bottleneck.
(a) (b)
Figure 5. Layout
Layout top
top views
views and
and device
device dimensions
dimensions of
of (a)
(a) conventional
conventional DCSCR;
DCSCR; and
and (b) proposed
ERTSCR. Both DCSCR and ERTSCR have a same device width of of 75
75 µm.
μm.
4. Experimental
4. Experimental Results
Results and
and Discussion
Discussion
4.1. TLP and HBM Results
4.1. TLP and HBM Results
The quasi-static I-V characteristics of the conventional DCSCR and proposed ERTSCR are measured
The quasi-static I-V characteristics of the conventional DCSCR and proposed ERTSCR are
using the transmission line pulse (TLP) HANWA TED-T5000 tester, with a rise time of 10 ns and pulse
measured using the transmission line pulse (TLP) HANWA TED-T5000 tester, with a rise time of 10
width of 100 ns. Figure 6 shows the TLP I-V curves of the conventional DCSCR and proposed ERTSCR
ns and pulse width of 100 ns. Figure 6 shows the TLP I-V curves of the conventional DCSCR and
with the same device width of 75 µm. Firstly, it can be observed that the trigger voltage (Vt1 ) of ERTSCR
proposed ERTSCR with the same device width of 75 μm. Firstly, it can be observed that the trigger
(1.33 V) is lower than that of DCSCR (1.48 V), which is due to the different trigger current distribution.
voltage (Vt1) of ERTSCR (1.33 V) is lower than that of DCSCR (1.48 V), which is due to the different
As shown in Figure 3a, the trigger current of the conventional DCSCR flows sideways along the diode
trigger current distribution. As shown in Figure 3a, the trigger current of the conventional DCSCR
chain conduction path from the anode to anode gate before flowing from the cathode gate to cathode,
flows sideways along the diode chain conduction path from the anode to anode gate before flowing
which deviates from the direction of SCR path. As a result, less carriers will be injected to WELLs
from the cathode gate to cathode, which deviates from the direction of SCR path. As a result, less
to trigger the SCR. However, the trigger current of the proposed ERTSCR flows inwardly along the
carriers will be injected to WELLs to trigger the SCR. However, the trigger current of the proposed
diode chain conduction path as illustrated in Figure 4a from the anode to deeper DNW in the same
ERTSCR flows inwardly along the diode chain conduction path as illustrated in Figure 4a from the
direction as SCR path. Therefore, more carriers will be injected to WELLs, which is more convenient
anode to deeper DNW in the same direction as SCR path. Therefore, more carriers will be injected to
for triggering SCR. Secondly, it can also be observed that the holding voltage (Vh ) of ERTSCR (1.06 V)
WELLs, which is more convenient for triggering SCR. Secondly, it can also be observed that the
is lower than that of DCSCR (1.32 V), which is due to the different current distribution of diode chain
holding voltage (Vh) of ERTSCR (1.06 V) is lower than that of DCSCR (1.32 V), which is due to the
conduction path and main SCR conduction path. When DCSCR and ERTSCR have been triggered,
different current distribution of diode chain conduction path and main SCR conduction path. When
the ESD current flows through both the diode chain conduction path and main SCR conduction path.
DCSCR and ERTSCR have been triggered, the ESD current flows through both the diode chain
In ERTSCR, the diode chain conduction path and main SCR conduction path overlap in NWELL-DNW.
conduction path and main SCR conduction path. In ERTSCR, the diode chain conduction path and
Thus, the holding voltage is mainly determined by the main SCR conduction path, which has a deeper
main SCR conduction path overlap in NWELL-DNW. Thus, the holding voltage is mainly determined
snapback and lower holding voltage. Finally, the second breakdown currents of both conventional
by the main SCR conduction path, which has a deeper snapback and lower holding voltage. Finally,
DCSCR and proposed ERTSCR are both approximately 5.3 A. Additionally, the human body model
the second breakdown currents of both conventional DCSCR and proposed ERTSCR are both
(HBM) measurement results show that both the conventional DCSCR and proposed ERTSCR have a
approximately 5.3 A. Additionally, the human body model (HBM) measurement results show that
HBM ESD robustness of more than 8 KV as measured using HANWA TED-W5000M. That means the
both the conventional DCSCR and proposed ERTSCR have a HBM ESD robustness of more than 8
proposed ERTSCR with a silicon area that is smaller by 10% has the same ESD robustness and can be
KV as measured using HANWA TED-W5000M. That means the proposed ERTSCR with a silicon
regarded as an area efficient structure compared to the conventional DCSCR.
area that is smaller by 10% has the same ESD robustness and can be regarded as an area efficient
structure compared to the conventional DCSCR.
Electronics 2019, 8, 445 66 of
of 8
Electronics 2019, 8, 445 6 of 8
Figure
Figure 6.
6. Measured
Measured TLP
TLP I-V
I-V curves
curves of
of conventional
conventional DCSCR
DCSCR and
and proposed
proposed ERTSCR.
ERTSCR.
Figure 6. Measured TLP I-V curves of conventional DCSCR and proposed ERTSCR.
4.2. VF-TLP
VF-TLP Measurement
Measurement and and Results
4.2. VF-TLP Measurement and Results
Another very fast TLP (VF-TLP) measurement was used to evaluate the turn-on performance of
Another very device fast TLP (VF-TLP) measurement was asused to evaluate the turn-on performance of
the ESD
ESD protection
protection deviceduringduringthe thefast
fastESD
ESD stress, such
stress, such as in the charged
in the chargeddevice model
device (CDM).
model (CDM).In this
In
the ESD
paper, protection
the pulse device
widthwidth during
of VF-TLP the fast ESD
pulse ispulse stress,
10 nsisand such as in the charged device model (CDM). In
this paper, the pulse of VF-TLP 10 the rise time
ns and the riseis 200
timeps.isFigure
200 ps.7 shows
Figurethe measured
7 shows the
this paper,
VF-TLP I-V the pulseand
curves width
the of VF-TLPvoltage
transient pulse iswaveforms
10 ns and the in riseholding
the time is region
200 ps.of Figure
the 7 shows the
conventional
measured VF-TLP I-V curves and the transient voltage waveforms in the holding region of the
measured
DCSCR andVF-TLP
proposed I-V curves and the transient results
voltageshow waveforms the in the holding regionDCSCR
of the
conventional DCSCR ERTSCR.
and proposed The measurement
ERTSCR. The measurement that results
overshoot voltages
show that the of
overshoot
conventional
and ERTSCR DCSCR
at 0.5 Aandand proposed
areERTSCR
4.34 V and ERTSCR.
6.15AV,are The measurement
respectively. results show that the overshoot
voltages of DCSCR at 0.5 4.34 V andThe 6.15overshoot voltageThe
V, respectively. of ERTSCR
overshoot is slightly
voltage
voltages
higher of DCSCR
than isthat and
of DCSCR ERTSCR
due at
to the 0.5 A are 4.34 V and 6.15 V, respectively. The overshoot voltage
of ERTSCR slightly higher than thatincreasing
of DCSCRresistance
due to the in increasing
the trigger resistance
path that isinintroduced
the triggerusing
path
of ERTSCR
RDNW is slightly higher than that of DCSCR due to the increasing resistance in the trigger path
that is. introduced
However, the overshoot
using voltage ofthe
RDNW. However, ERTSCR is low
overshoot enough
voltage of to protectisthe
ERTSCR lowinternal
enough circuit from
to protect
that is
the fast introduced
ESDcircuit
damage using
evenR DNW. However, the overshoot voltage of ERTSCR is low enough to protect
internal from theinfast
the ESD
nanometer
damagescaleevenprocess [17].
in the nanometer scale process [17].
the internal circuit from the fast ESD damage even in the nanometer scale process [17].
Measured VF-TLP I-V curves and transient voltage waveforms of conventional DCSCR and
Figure 7. Measured
Figure 7. Measured
proposed ERTSCR. VF-TLP I-V curves and transient voltage waveforms of conventional DCSCR and
ERTSCR.
proposed ERTSCR.
4.3. Leakage Current Characteristics
4.3. Leakage Current Characteristics
4.3. Leakage Current Characteristics
Leakage current
Leakage current is
is another
another critical
critical design
design metric
metric for
for the
the ESD
ESD devices
devices [18,19]. Figure 88 shows
[18,19]. Figure shows the
the
Leakage
measured leakage current is another critical design metric for the ESD devices [18,19]. Figure 8 shows the
measured leakage currents
currents of the conventional
of the conventional DCSCR
DCSCR and and proposed
proposed ERTSCR,
ERTSCR, with
with the anode biased
the anode biased
measured
from 00 V leakage currents of the conventional DCSCR andthat
proposed ERTSCR, withare
theless
anode biased
from V to
to1.6
1.6VVand
andthe
thecathode
cathodegrounded.
grounded.It Itcan
canbebe
seen thethe
seen that leakage currents
leakage currents than
are less 1 µA
than 1
from 0biased
when V to 1.6 V and
below 1.2the
V, cathode
which grounded.
shows that It can
both be seenare
structures thatsuitable
the leakage
for currents
the ESD are less than
protection of 1
the
μA when biased below 1.2 V, which shows that both structures are suitable for the ESD protection of
μA when biased below 1.2 V, which shows that both structures are suitable for the ESD protection of
Electronics 2019, 8, 445 7 of 8
Electronics 2019, 8, 445 7 of 8
the working
ICs ICs working at V
at 1.2 1.2orVbelow
or below [20].
[20]. AsAs
thethe biased
biased voltage
voltage continuouslyincreases,
continuously increases,both
boththe
theleakage
leakage
currentsquickly
currents quicklyincrease
increasewith
withthe
theturning
turningononofofthe
thetwo
twodiodes
diodesand
andfollowing
followingSCR.
SCR.
Figure 8. Measured
Figure8. Measured leakage
leakage currents
currentsof
ofconventional
conventionalDCSCR
DCSCRand
andproposed
proposedERTSCR.
ERTSCR.
5. Conclusions
5. Conclusions
An ESD protection device is presented in this article as an embedded resistor-triggered SCR.
An ESD protection device is presented in this article as an embedded resistor-triggered SCR. The
The proposed ERTSCR has a low trigger voltage, high second breakdown currents and acceptable
proposed ERTSCR has a low trigger voltage, high second breakdown currents and acceptable leakage
leakage current. With comparable ESD robustness to conventional DCSCR, the proposed ERTSCR has
current. With comparable ESD robustness to conventional DCSCR, the proposed ERTSCR has a wider
a wider top metal width and an area cost reduction of approximately 10%.
top metal width and an area cost reduction of approximately 10%.
Author Contributions: Conceptualization, F.H. and Z.L.; methodology, F.H. and F.D; software, K.Y. and J.L.;
Author Contributions:
validation, F.H., F.D. andconceptualization, F.H. K.Y.;
K.Y.; formal analysis, and Z.L.; methodology,
investigation, F.H.F.D;
F.H. and andresources,
F.D; software, K.Y.curation,
J.L.; data and J.L.;
F.H.; writing—original
validation, draft
F.H., F.D. and preparation,
K.Y.; F.H.; writing—review
formal analysis, and
K.Y.; investigation, editing,
F.H. J.L. resources,
and F.D; and Z.L.; visualization, J.L.;
J.L.; data curation,
supervision, Z.L.
F.H.; writing—original draft preparation, F.H.; writing—review and editing, J.L. and Z.L.; visualization, J.L.;
Funding: ThisZ.L.
supervision, research was funded by the Nature Science Foundation of China 61874098, Central Universities
Fundamental Research Project ZYGX2018J025 and Sichuan Science and Technology Basic Condition Platform
Project 18PTDJ0053.
Funding: This research was funded by the Nature Science Foundation of China 61874098, Central Universities
Fundamental
Conflicts Research
of Interest: TheProject
authorsZYGX2018J025 and Sichuan
declare no conflict Science and Technology Basic Condition Platform
of interest.
Project 18PTDJ0053.
References
Conflicts of Interest: The authors declare no conflict of interest.
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