Computer Architecture Lecture 01 - Introduction - Pengju Ren Institute of Artificial Intelligence and Robotics
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Computer Architecture
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Lecture 01 - Introduction U
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n g of Artificial Intelligence and Robotics
Pe Xi’an Jiaotong University
Institute
http://gr.xjtu.edu.cn/web/pengjuren
Course Administration
Instructor: Pengju Ren
TA: Gelin Fu （Ph.D Candidate)
Lectures: Two 100-minute lectures a week
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Textbook: Computer Architecture: A Quantitative Approach
6th Edition(2019)J T U
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Prerequisite: Digital System Structure and Design
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Preface
“The most beautiful thing we can experience is the
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mysterious. It is the source of all true art and Science.”
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0 I believe, 1930
---Albert Einstein,2What
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What is Computer Architecture
Application
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2 0 computer
In its broadest definition,
architecture Tis U
the design of the
Gap too large to X J
abstraction/Implementation layers
@ us to implement information
thatnallow
bridge in one step
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processing applications efficiently
gj u using available manufacturing
e n technologies.
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Physics
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What is Computer Architecture
Application
Algorithm 2 1
Programming Language 20
Operating System/Virtual Machines J TU
Gap too largeSet
Instruction to Architecture (ISA)
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bridge in one step
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Microarchitecture
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Register-Transfer Level (RTL)
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Gates
PCircuits
Devices
Physics
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What is Computer Architecture
Application
Algorithm 2 1
Programming Language 2 0
Operating System/Virtual Machines J TU
Gap too largeSet
Instruction to Architecture (ISA)
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bridge in one step
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Microarchitecture
j u R This course
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Register-Transfer Level (RTL)
e
Gates
PCircuits
Devices
Physics
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What is Computer Architecture
Application Application Requirement:
Algorithm 2 1
Suggest how to improve
Programming Language 2 0
architecture
Provide revenue to fund
Operating System/Virtual Machines J T U
development
Gap too largeSet
Instruction to Architecture (ISA)
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bridge in one step
e nArchitecture provides feedback to
Microarchitecture
j u R guide application and technology
research directions
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Register-Transfer Level (RTL)
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Gates
PCircuits Technology Constraints:
Restrict what can be done efficiently
Devices New technologies make new arch
Physics possible
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Computing Devices Then…
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EDSAC, University of Cambridge, UK, 1949
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Computing Devices Now
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Modern computing is as much
about enhancing capabilities as
data processing!
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Architecture continually changing
Applications suggest Improved
technologies make
how to improve
Applications 2 1
new applications
technology, provide
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revenue to fund
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development
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Technology
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makes compatibility a major
force in market
10Single-Thread(Sequential) Processor Performance
Mulitcore or ManyCore
[ Hennessy & Patterson, 2017 ]
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RISC
11Moore’s Law Scaling with Cores
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12Global Semiconductor Market
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The global semiconductor market is estimated at $450 billion USD in revenue for 2020.
Products using these semiconductors represent global revenues of $2 trillion USD, or
around 3.5% of global gross domestic product (GDP)
ISSCC2021‘Feb 13Advanced Tech nodes continue provide value
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Steady progress in two-dimensional transistor scaling and a variety of device
enhancement techniques have sustained energy-efficiency improvement and device
density gains from one technology generation to the next
ISSCC2021‘Feb 14Upheaval in Computer Design
• Most of last 50 years, Moore’s Law ruled
– Technology scaling allowed continual performance/energy
improvements without changing software model
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• Last decade, technology scaling slowed/stopped 2 0
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– Dennard (voltage) scaling over (supplyTvoltage ~fixed)
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– Moore’s Law (cost/transistor) over?
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– No competitive replacementn for CMOS anytime soon
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– Energy efficiency constrains
j everything
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• No “free lunch” g for software developers, must
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consider:
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– Parallel systems
– Heterogeneous systems
15Today’s Dominant Target Systems
• Mobile (smartphone/tablet)
– >1 billion sold/year
in system-on-a-chip (SoC)
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– Market dominated by ARM-ISA-compatible general-purpose processor
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– Plus sea of custom accelerators (radio, image, video, graphics, audio,
motion, location, security, etc.)
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• Warehouse-Scale Computers (WSCs)
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–
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100,000’s cores per warehouse
–
–
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Market dominated by x86-compatible server chips
Dedicated apps, plus cloud hosting of virtual machines
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Now seeing increasing use of GPUs, FPGAs, custom hardware to
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accelerate workloads
• Embedded computing
– Wired/wireless network infrastructure, printers
– Consumer TV/Music/Games/Automotive/Camera/MP3
– Internet of Things!
16Course Content Computer Architecture
• Instruction Level Parallelism
– Superscalar
– Very Long Instruction Word (VLIW)
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• Advanced Memory and Caches
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• Data Level Parallelism
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– Vector Machine
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– GPU
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• Thread Level Parallelism
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– Multithreading
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– Multiprocessor/Multicore/ManyCore
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• Warehouse-Scale Computers (Request Level Paral.)
• Domain-Specific Architectures (DNN Accelerator)
Intel Nehalem Processor, Core i7
17Architecture vs. Microarchitecture
“Architecture”/Instruction Set Architecture:
Programmer visible state (Memory & Register)
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Operations (Instructions and how they work)
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Execution Semantics (interrupts)
Input/Output J T U
Data Types/Sizes @ X
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Microarchitecture/Organization:
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Tradeoffs on how
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to implement ISA for some metric
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n Cost)
(Speed,eEnergy,
P Pipeline depth, number of pipelines, cache
Examples:
size, silicon area, peak power, execution ordering, bus
widths, ALU widths
18Same Architecture Diff Micro-Architecture
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19Diff Architecture Diff Micro-Architecture
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20Where do Operands come from and
Where do Results Go ?
Processor
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ALU
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MEMORY
…
21Where do Operands come from and
Where do Results Go ?
Stack Accumulator Reg-Mem Reg-Reg
Processor
Processor
Processor
Processor
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ALU ALU
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ALU ALU
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MEMORY
MEMORY
MEMORY
MEMORY
… … … …
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22Where do Operands come from and
Where do Results Go ?
Stack Accumulator Reg-Mem Reg-Reg
Processor
Processor
Processor
Processor
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ALU ALU
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ALU ALU
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MEMORY
MEMORY
MEMORY
MEMORY
… … … …
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Number Explicitly
0 1 2 or 3 2 or 3
Named Operands
23Stack-Based Instruction Set Architecture(ISA)
Stack
Burrough’s B5000 (1960)
Processor
• Burrough’s B6700
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• HP 3000
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ALU
• ICL 2900
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• Symbolics 3600
• Inmos Transputer
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Modern
• Forth machines
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MEMORY
…
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• Intel x87 Floating Point Unit
24Evaluation of Expressions
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25Evaluation of Expressions
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26Evaluation of Expressions
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27Evaluation of Expressions
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28Evaluation of Expressions
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29Evaluation of Expressions
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30Evaluation of Expressions
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31Evaluation of Expressions
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32Hardware Organization of the Stack
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Stack is part of the processor state 2 0
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stack must be bounded and small
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≈ number of Registers, not the size of main memory
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Conceptually stack is unbounded
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a part of the stack is included in the
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processor state; the rest is kept in the main memory
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33Stack Operations/Implicit Memory References
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Suppose the top 2 elements of the stack are kept in registers and
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the rest is kept in the memory.
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Each push operation 1 memory
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pop operation 1@ X
memory reference
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Better performance byjkeeping the top N elements in registers, and
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memory referencesnare made only when register stack overflows or
underflows. P e
34Stack Size and Memory References
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Four Store and Fetch
35Stack Size and Memory References
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36Where do Operands come from and
Where do Results Go ?
Stack Accumulator Reg-Mem Reg-Reg
Processor
Processor
Processor
Processor
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ALU ALU
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ALU ALU
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MEMORY
MEMORY
MEMORY
MEMORY
… … … …
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Push A Load R1, A
Load A Load R1 A
C= A+B Push B Load R2, B
Add B Add R3 R1, B
Add Add R3, R1, R2
Store C Store R3, C
Pop C Store R3, C 37Classes of Instructions
• Data Transfer
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– LD, ST, MFC1, MTC1, MFC0, MTC0
• ALU 2 0
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– ADD, SUB, AND, OR, XOR, MUL, DIV, SLT, LUI
• Control Flow X
@ERET
• Floating Point Re
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– BEQZ, JR, JAL, TRAP,
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– ADD.D, SUB.S, MUL.D, C.LT.D, CVT.S.W,
e n (SIMD)
• Multimedia
P SUB.PS, MUL.PS, C.LT.PS
– ADD.PS,
• String
– REP MOVSB (x86)
38Addressing Modes: How to get operands from
Memory (MIPS)
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** May not actually access memory 39ISA Encoding
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40Case study: X86(IA-32) Instruction Encoding
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41RISC-V Instruction Encoding(1)
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42RISC-V Instruction Encoding(2)
New open-source, license-free
ISA spec
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• Supported by growing shared 2 0
software ecosystem
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• Appropriate for all levels of
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computing system, from n
microcontrollers to
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supercomputers
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• 32-bit, 64-bit, and 128-bit
variants (we’re using 32-bit in
class, textbook uses 64-bit)
http://www-inst.eecs.berkeley.edu/~cs61c/fa18/img/riscvcard.pdf 43Real World Instruction Sets
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44Why the Diversity in ISAs?
Application Influenced ISA
• Instructions for Applications
– DSP instructions 2 1
• Compiler Technology has improved 2 0
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– SPARC Register Windows no longer needed
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– Compiler can register allocate effectively
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eISA
Technology Influenced
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• Storage is expensive, tight encoding important
n Set Computer
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• Reduced Instruction
– Remove instructions until whole computer fits on die
• Multicore/Manycore
– Transistors not turning into sequential performance
45Recap
Application
Algorithm 2 1
Programming Language 2 0
ISA vs Micro-Architecture
ISAUCharacteristics
Operating System/Virtual Machines
XJ T
• Machine Models
Gap too largeSet
to Architecture (ISA)
Instruction
n @ • Encoding
bridge in one step
Microarchitecture
R e
g j u
Register-Transfer Level (RTL)
• Data Types
e n
Gates • Instructions
PCircuits • Addressing Modes
Devices
Physics
46And in conclusion …
• Computer Architecture >> ISAs and RTL
• Computer Architecture is about interaction of
hardware and software, and design of appropriate 2 1
abstraction layers 2 0
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• Computer architecture is shaped by technology and
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applications
– History provides lessonsR
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for the future
• Computer Science j u
g at the crossroads from sequential
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to parallelPcomputing
– Salvation requires innovation in many fields, including computer
architecture
• Read Chapter 1 & Appendix A for next time! (6th)
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Next Lecture： RISC-V ISA, Datapath
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48Acknowledgements
• Some slides contain material developed and copyright by:
– Arvind (MIT)
– Krste Asanovic (MIT/UCB)
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– Joel Emer (Intel/MIT)
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– James Hoe (CMU)
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–
David Patterson (UCB)
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David Wentzlaff (Princeton University)
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• MIT material derived
j Rfrom course 6.823
g from course CS252 and CS 61C
• UCB materialnderived
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49Idealized Uniprocessor Model
Processor names variables:
– Integers, floats, pointers, arrays, structures, etc.
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– These are really words, e.g., 64-bit double, 32-bit INTs, bytes, etc.
2
Processor performs operations on those
J T U variables:
– Arithmetic, logical operations, etc.X
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– Only performs these operations
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Processor controls the
g j u order, as specified by program
– Branches(if), e n
loops(while), function calls, etc.
Idealized Cost
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– Each operation has roughly the same cost: add, multiply, etc.
502 1
Six Great Ideas in Computer U 20
Architecture
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51New School Machine Architecture
• Parallel Requests
Software Hardware
2 1
Assigned to computer Harness
Warehouse
Scale
2 0 Smart
Phone
e.g., Search “Cats” Parallelism &
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Computer
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• Parallel Threads
Assigned to core
Achieve High
@X Computer
e.g., Lookup, Ads
Performance
en Core … Core
• Parallel Instructions
j u R Memory (Cache)
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>1 instruction @ one time
Input/Output
Instruction Unit(s)
Core
Functional
• Parallel Data
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e.g., 5 pipelined instructions
P Unit(s)
A0+B0A1+B1A2+B2A3+B3
>1 data item @ one time Main Memory
e.g., Add of 4 pairs of words Logic Gates
• Hardware descriptions
All gates working in parallel at same time
52Great Idea #1: Abstraction
(Levels of Representation/Interpretation)
High Level Language temp = v[k];
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Program (e.g., C)
Compiler
v[k] = v[k+1];
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Assembly Language
J
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v[k+1] = temp; Anything can be represented
$t0, 0($2) as a number,
Program (e.g., RISC-V)
Assembler
@X
lw
sw
sw
$t1, 4($2)
$t1, 0($2)
$t0, 4($2)
i.e., data or instructions
Machine Language
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1000 1101 1110 0010 0000 0000 0000 0000
Program (RISC-V)
Machine
j u 1000 1110 0001 0000 0000 0000 0000 0100
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Interpretation 1010 1110 0001 0010 0000 0000 0000 0000
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Hardware Architecture Description 1010 1101 1110 0010 0000 0000 0000 0100
(e.g., block diagrams)
Architecture
Implementation
Logic Circuit Description
(Circuit Schematic Diagrams)
53Great Idea #2: Moore’s law
(Technique driven development)
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54Great Idea #3: Principle of Locality/
Memory Hierarchy
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55Great Idea #4: Parallelism
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562 1
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Computer Pioneer
Amdahl’s Law
57Great Idea #5: Performance Measurement
and Improvement
• Matching application to underlying hardware
to exploit: 2 1
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– Locality
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– Parallelism
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– Special hardware features, like specialized instructions
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(e.g., matrix manipulation)
• Latency
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– How long to set the problem up
– How much faster does it execute once it gets going
– It is all about time to finish
58Great Idea #6: Dependability via Redundancy
• Redundancy so that a failing piece doesn’t make the whole 2 1
system fail 2 0
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1+1=2X 2 of 3 agree
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1+1=2 1+1=2 1+1=1 FAIL!
Increasing transistor density reduces the cost of redundancy
59Great Idea #6: Dependability via Redundancy
• Applies to everything from datacenters to 2 1
storage to memory to instructors 2 0
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– Redundant datacenters so that can lose 1
datacenter but Internet service stays online
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– Redundant disks so that can lose 1 disk but not lose
data (Redundant Arrays of Independent Disks/RAID)
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– Redundant memory bits of so that can lose 1 bit but
no data (Error Correcting Code/ECC Memory)
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