Granite River Labs & Silicon-IP - High Speed Interface IP Qualification-Pitfalls & Best Practices
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Granite River Labs & Silicon-IP High Speed Interface IP Qualification- Pitfalls & Best Practices GRL Company Confidential
Complex Test Methodologies
More Equipment
Higher Costs
Test
Equipment
Signal
Integrity GRL Customer
Adopt new technologies
Meet product schedules
Interface
Standards Debug and improve quality
Higher Speeds
More Diversity
Constant Changes
GRL Company Confidential
GRL Company Snapshot
Help customers adopt new high speed interfaces through signal
integrity & testing services
Signal Integrity Modeling & Consulting
Initial Bring-up, Debug, & Stress Testing
Final Compliance Certification
Full range of equipment & experts
High performance real-time scopes, BERT’s, AWG’s and VNA/TDR’s
Full range of protocol analyzers and interoperability test beds
Recognized experts in signal integrity and compliance testing
Convenient test locations
Santa Clara, California, USA
Taipei, Taiwan & Hsinchu, Taiwan
Boeblingen, Germany
3
The Need for Speed
Telecom, Datacom, & Enterprise data rates continue their
unrelenting march higher
30
Gbs
25
Telecom/Datacom/Enterprise
SAS
20
Infiniband x1
Fibre Channel
15 Interlaken x1
XAUI x1
XFP
10
SFP/SFP+
Ethernet
5 CEI x1
0
1995 2000 2005 2010 2015 2020
GRL Company Confidential 4
The Need for Speed
But 3-10Gbs speeds are now the norm in PC and Consumer
markets with all have plans to double data rates
18
Gbs Enterprise/
16
Datacom/Telecom
14 Sweet Spot
12
PCIe x1
10 USB
SATA
8 1394
Thunderbolt
6
DisplayPort x1
4
2
0
1995 2000 2005 2010 2015 2020
GRL Company Confidential 5
Standards Get Faster & Proliferate
Mobile DP (MyDP)
MHL 3.0
HDMI 2.0
SD 4.0 UHS-2
MPHY
UniPro
DigRF
DDR4
(8GTs) (16GTs)
(? Gbs)
(? Gbs)
SSIC
(12Gbs)
SOP
(32Gbs)
(2010) (2011) (2012) (2013) (2014) (2015)
GRL Company Confidential 6
R&D/IP costs increasing with smaller
process nodes- IP mistakes too costly
(source JRC, 2009)
GRL Company Confidential 7
Challenges with Higher Speed
Interfaces & Smaller Process Nodes
Higher speed results in tighter timing budgets to work with and
tougher compliance specs to meet
At smaller process geometries, PVT can have a big impact on
reducing timing/voltage margin and closing eyes
GRL Company Confidential 8
Signal Integrity Challenges with
High Speed
Signal loss over distance gets worst with speed, closing the eye
Performance more susceptible to jitter due to small time
budgets associated with higher speeds
Jitter can come from anywhere
Transmitter or physical media bandwidth limitations
Improper impedance termination and physical media
discontinuities
Clock asymmetries in rise and fall times
Power supply cross coupling with data or clock lines
EMI issues
GRL Company Confidential
Increased Specialization &
Knowledge/Resource Gaps
Proper evaluation of high speed interface IP has become very
specialized
Common Knowledge & Resource Gaps
SOC team dependence on External or Internal IP suppliers
SOC team lack of detailed understanding of IP
IP Supplier and SOC team lack detailed understanding of standards
compliance and what’s required to test device for compliance
Standards groups usually define compliance standards and testing
methodologies for final products and not silicon
Test equipment needed for high speed interface testing is very
costly (>$.5mil) and complex
GRL Company Confidential 10Common Real-World Problems
Seen by GRL
SOC team has adopted “Silicon Proven” IP
Did not request or review compliance reports from IP vendor
Did not perform adequate validation post silicon
SOC team had assumed IP was ready to go
Device comes to GRL and fails compliance testing miserably
Results- months of debug, re-spins, and unnecessary expense
High Speed Interface IP can’t be tested
Because of a lack of understanding of compliance testing, required
test modes and compliance patterns not enabled
IP vendor tested before using their own test methodology instead of
what is required for compliance
Results- months of working with IP vendor to debug and enable test
modes and patterns with no test results possible in the meantime
GRL Company Confidential 11
Delays in starting to testCommon Real-World Problems
Seen by GRL
“Silicon IP” vendor absolves responsibility for compliance
testing
SOC team bears the burden of trying to figure out IP design,
debugging, determine compliance tests required, etc.
Minimal support from IP vendor in helping to get SOC product
certified
Results- months of debug, re-spins, and unnecessary expense
PVT characterization and stress testing exposes real-world
potential issues
Without proper tuning, sub-65nm IC’s fail to meet compliance specs
for at least 30-40% of all PVT variations
Tuning is a lengthy involved process and may take several weeks
Close teamwork between IP vendor, SOC team, and testing team
needed to identify and resolve issues
GRL Company Confidential 12Common Real-World Problems
Seen by GRL
PVT characterization and stress testing skipped because of
budget constrains or lack of awareness
Validation testing has essentially been pushed to be the
responsibility of the customer
Customers may observe severe failures under different
unpredictable environmental conditions
Result- loss of credibility, sales, and switching to competition
GRL Company Confidential 13IP Technical Due Diligence-
Compliance Testing Primer
Compliance tests developed by company or standards body
to enforce product spec conformity in order to achieve
interoperability between products
Often directly enforced through technology license
agreements, logo usage rights, and sales rights
Brand OEM companies usually demand that their products
pass compliance
Most compliance standards are geared towards final system
products even though silicon and IP companies bear much of
the burden for meeting compliance
GRL Company Confidential 14IP Technical Due Diligence- Need
to Understand Compliance Testing
Understand what products, test items, and specs compliance
testing covers
Compliance tests may not cover certain product types (e.g. USB 3.0
embedded hosts)
Receiver testing and return loss may be optional for compliance
testing but still recommended
Many compliance tests are to CEM (Card Electromechanical) spec
while often silicon is tested to the Base spec
Understand test equipment, tools, and software used for
compliance
Need to work with equipment, tools, and fixtures approved by
standards bodies
Some equipment and tools may not longer be commercially
available
GRL Company Confidential 15IP Technical Due Diligence- Can
Compliance Testing be Performed?
Certain DUT (Device Under Test) behavior needed for
compliance testing to be feasibly or cost effectively done
To perform testing, DUT’s need to be able to output data
patterns on which to perform measurements
Compliance testing (particularly receiver tests) require DUT to
support specific loopback modes
Compliance testing may require use of lower speed
communication channels and ability to turn off encryption
Hooks into DUT often needed to enable coordination between
test sequencing and DUT behavior
Compliance testing requires access to clean signals and may
require use of specific interface connectors
GRL Company Confidential 16IP Technical Due Diligence- Beyond
Compliance Testing
PVT Characterization Testing Services
Run compliance tests over different process split lots, voltage, and
temperature conditions
Run stress tests to determine point of failure by adjusting frequency,
jitter, voltage, and other parameters
Use IC customer’s tools to tune SERDES settings and debug
compliance failures and optimize test margins
Link Layer/Protocol Stress Testing Services
Identify areas where DUT fails to meet standards specification
Identify possible real world conditions where DUT may fail or cause
unacceptable behavior
Work with customer to determine test coverage and matrix
GRL Company Confidential 17You can also read
