Scientific & technical highlights 1 - 2020 EDITION - IRT Nanoelec
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1
Scientific
& technical
highlights
2020 EDITION
“ The technological research
institute IRT Nanoelec is a
consortium of 21 members
from the private and public
sectors dedicated to innovation
in microelectronics.
© CEA/Avanian
3
Table of contents
4 18 54
Delving into 3D Human capital
the heart of Integration and education
microelectronics
of the future design
IRT Nanoelec
activities
at a glance
28
Silicon 62
photonics
6 Large-scale
Key figures of instruments
the institute characterisation
December 2019 36
Pulse
68
8 Easytech
Digital as 48
an option
for resilience PowerGaN
Director’s Foreword
10
Highlights Scientific & technical highlights of the IRT Nanoelec • 2020 EDITION
Director of publication: Hughes Métras
Writing and editing: François Legrand & Eric Rouchouze, with Sandrine Maubert
English Translation: Provence Traduction
Layout: Supernova
Grenoble, June 2020
4
> Delving into the heart
of microelectronics of
the future
IRT Nanoelec at a glance
IRT Nanoelec runs multi-partner
technology dissemination and
development programs to make
the microelectronics sector more
competitive.
The aim of IRT Nanoelec members is to work IRT Nanolec also has a training program to pre-
together to carry out research and development pare human capital for changes at its partner
programs to help businesses create value and organizations, and a technology dissemination
grow. program for SMEs and mid-caps. These two pro-
grams receive support from the French State and
Since 2012, 238 associated partners, including local authorities, among which the AURA region.
184 SMEs and 17 foreign companies have carried
out projects with Nanoelec. Nanoelec has been operational since 2012 and is
one of the eight technological research institutes
At Nanoelec, information and communication (IRT) launched as part of the Investments for the
technologies professionals work in the digital Future Program (PIA). These institutes are R&D
transition, energy transition and secure connec- operators, bringing together an ecosystem of
ted systems fields. public laboratories and private partners, each
with a specific focus on a technological field.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents
5
“
Work together to carry out
research and development
programs to help businesses
create value and grow.
Anticipating future human,
material and technological needs
> Innovation in > Technology > Development
Microelectronics Dissemination of Human Capital
• Carry out world-class • Develop and transfer these • Attract more young people
collaborative R&D in four main technologies to our partners, into jobs in electronics
areas: 3D integration tech- to create the electronic circuits
• Map out needs and assess
nologies, silicon photonics, of the future
employment opportunities
GaN-on-Si power components
• Help businesses in
and digital trust for embedded • Design training courses
the field of information
systems and components to meet current needs
and communication
• Give industry players access technologies meet the • Anticipate future skills
to development, prototyping challenges of IoT and required in the electronics
and advanced characterisation digital trust and security industry
resources
• Promote cooperation
between SMEs, mid-caps
and large companies
Table of contents IRT NANOELEC / 2020 EDITION • IRT Nanoelec at a glance
6
> Key figures
of the
institute
December 2019
A consortium of €60M
public annual budget
& private
members*
* 22 partners in december 2019
238 394
associated partners, scientific or technical
including 184 small publications &
& medium size communications
companies since 2015
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents
7
“ Anticipating future
human and technical
needs
POWERGAN
3D INTEGRATION
EASYTECH 15
46
29
173
patents and 36 31
software solutions PULSE
52
filed since 2012 PHOTONICS
Human resources at the Institute
(in Equivalent full-time)
IRT DIR
POWERGaN
HUMAN 3D INTEGRATION
6
49
269
CAPITAL &
TRAINING 65
ENGENEERING
13
full time jobs, EASYTECH 16
33% coming from 43
private companies 70 7 PHOTONICS
PULSE
CHARACTERISATION
Table of contents IRT NANOELEC / 2020 EDITION • Key figures from the institute
8
> Digital as an option
for resilience
Director’s Foreword
HUGHES METRAS From the start of confinement, while usual social
activities were abruptly reduced and our offices,
Director of the
shops, factories, movie theaters and streets were
Technological
emptied, the digital world took over and helped
Research Institute
us to keep in touch with our loved ones, friends,
IRT Nanoelec
partners and coworkers.
Digital technologies enabled many businesses
and economic actors to continue their operations
during this period of quarantine. These solutions
helped maintain the ties that are the very fabric
of our societies. The media hardly noticed it but
many activities carried on thanks to digital tech-
nology: virtual classes in education, TV programs,
“
health instructions and solidarity on radio chan-
nels, remote banking and contactless payments
The media hardly and, last but not least, the now famous teleconfe-
noticed it but many rences from our home offices are just examples
of the “digital experiences” that each of us lived in
activities carried the recent weeks.
on thanks to digital The coming world will bring accelerated changes,
most of which are based on digital tools. Connec-
technology. tivity and image technologies have proven particu-
larly essential in this context. Their use, at a scale
never seen before, also underlines the need for
continuous innovation in the field, towards more
efficient components and software with more ad-
vanced functionalities, endowed with artificial in-
telligence and deep learning functions.
Today, a few months after the outbreak of an
unprecedented health and economic crisis, the
electronics industry intends to meet the challen-
ges of recovery and economic sovereignty. Pro-
vided that the infrastructures on which they are
based evolve, semiconductor technologies could
be a solid pillar of the revival of the economy.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents
9
“ We confirmed our
ability to contribute
to the vitality of the We are a consortium at the interface between aca-
microelectronic
demic research, education and industry & services,
supported by the French Government 1. Above all,
sector in France and our impact and our results come from the excel-
lence of the teams engaged by all of our partners,
Europe by involving relying on a set of technological means that make
Grenoble a unique ecosystem in our fields.
more and more Browsing the last 18 months over the pages of this
innovative SMEs report, you will see that Nanoelec is continuously
evolving to keep up with the evolutions of the
and mid-caps. microelectronics sector. As an example, our 3D
and photonics programs, initially positioned on
disruptive solutions for computation are now also
adressing the field of sensors. Similarly, our Pulse
program continues its transition to cybersecurity,
placing us at the heart of the challenges of sove-
reignty and digital trust.
These considerations inspired us to choose a leaf
We have also confirmed our ability to contribute
of Gingko Biloba for the cover of this activity report.
to the vitality of the microelectronics in France
It is a perfect symbol of resilience. At Nanoelec, we
and Europe by involving more and more innovative
are convinced that innovation in electronics, car-
SMEs and mid-caps. The entry into the consor-
ried out in a multidisciplinary and multi-partner
tium of Akeoplus, Prophesee, Aledia and Lynred
framework, is one of the drivers of this resilience.
illustrates this as much as the numerous projects
Our mission is to implement new ideas.
carried out within the framework of Easytech, the
program also funded by the French region AURA
Upgrading our programs to an increasingly com-
and local institutions
petitive and multi-application environment will
require open innovation initiatives. This seems A little less than a year after taking office to pur-
particularly urgent and essential in fast changing sue the task of my predecessor Michel Wolny, I am
fields such as imaging technology which connects pleased to introduce this reflection of a very intense
the physical and digital worlds. It is also critical activity. The excellence of the results, as well as
in the field of energy conversion, so important for the extent and diversity of the subjects dealt with in
the electrification of transportation systems, or in this report, are a witness of the quality of the work
the domain of secure components and embedded carried out over the past eight years and I would
systems necessary for resilient and sovereign therefore like to thank Michel and his team who
infrastructures. accompanied me during these first months.
1
The French Government confirmed on Jun 4, 2020, its support to its 16 institutes dedicated to technological research and Energy transition, federated in the FIT Association.
Table of contents IRT NANOELEC / 2020 EDITION • Director’s Foreword
10
Highlights
NOVEMBER 2018
GaN workshop
> 70 innovation professionals from the
electronic sector take part in a national
workshop on GaN-based power components,
which was organized by Nanoelec in Paris.
OCTOBER 2018
Digital
transformation
> Akeoplus, a company involved in the digital
transformation of factories, specifically in
the automotive and aeronautical fields, joins
the Nanoelec consortium.
JANUARY 2019
Semi 3D
Summit
> Developed under
Nanoelec, IntAct, an active
interposer demonstrator for
High performance computing
(HPC), and Harmony, the
world’s first demonstrator of
© Semi Europe
a 3D integrated image sensor
with a pitch of 1.44 micron,
are presented to 200 partici-
pants at the Semi 3D Summit
in Germany.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents11
JANUARY 2019
Characterisation
platform
> The PAC-G characterisation platform
is presented to Jean-Eric Paquet,
General Manager for research and innovation
at the European Commission.
FEBRUARY 2019
Lean Management
> Official launch of RNDYNEO, a training
in Lean Management applied to R&D.
© GEM
FEBRUARY 2019
Photonics
West
> Nanoelec presents a
photonic fiber-chip coupling
by nano-structurednetwork
with only 1 dB of optical
© Desmond Talkington
losses, at the Photonics West
conference (USA).
MARCH 2019
General
Assembly
> 150 participants
© Nanoelec
attend IRT Nanoelec’s
general assembly.
Table of contents IRT NANOELEC / 2020 EDITION • Highlights12
MAY 2019
Immersive
learning space
> First version of the “TIM Lab” (GEM),
an immersive learning space dedicated to
the management of innovation and technology
that fosters collective intelligence and
“phygital” tools.
© CEA
© GEM Labs
MAY 2019
Award
> “Best Paper Award” at the ECTC
conference (May 2019, Las Vegas, USA)
for his article entitled “Active Interposer
JUNE 2019 Technology for Chiplet-Based Advanced
3D 3D System Architectures”.
integration
> Aledia, a start-up involved in 3D LED
technology, and Prophesee, a neuromorphic
imaging system start-up, join the Nanoelec JUNE 2019
consortium to participate in the 3D integration
program.
Digital Tech for care
> Samba, a software and hardware solution
for welcoming hearing-impaired students
to university, offers fast and smooth speech
transcription that staff at the front desk can
correct or enhance in real time.
© CEA
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents13
SEPTEMBER 2019
Semicon
Taiwan
> SET launches the new NEO HB hybrid
bonding machine at Semicon Taiwan.
© SET
NeoHB was developed through
the Nanoelec/3D integration program.
SEPTEMBER 2019
Powergan consortium
> G2ELab joins the Nanoelec/Powergan
consortium, bringing its expertise
on electromagnetic compatibility.
© G2Elab
SEPTEMBER 2019
SEPTEMBER 2019
Management
Sport > Hugues Métras is
trade fair appointed Director
© Jayet / CEA
of the institute, taking
> Nanoelec/EasyTech over from Michel Wolny.
and the SMEs, Ido Data and
Microoled jointly participate
to the Sport Unlimitech trade
fair, in Lyon.
SEPTEMBER 2019
Power electronics
> STMicroelectronics invests e100 million in a pilot line
for power electronics, based on a technology developed as part
of Nanoelec.
© STmicroelectronics
Table of contents IRT NANOELEC / 2020 EDITION • Highlights14
SEPTEMBER 2019
Starting-up
Photonics
> Scintil Photonics,
a start-up that integrates
photonic technologies
developed as part of
Nanoelec, raises
e4 million during a first © CEA/D. Morel
round of funding.
OCTOBER 2019
3DVLSI
workshop
OCTOBER 2019 > Around 60 professionals
RISC-V participate in the sixth
3DVLSI workshop
forum (high-density 3D-IC and
CoolCube technologies)
> 120 participants attend organized by CEA-Leti,
the RISC-V forum organized NanoElec and Qualcomm,
by Nanoelec in Paris. RISC-V on the sidelines of the IEEE
© Nanoelec
is the international standard 2019 S3S conference.
for open architecture in
electronics industry.
Table of co
OCTOBER 2019
Forum for the
institutes of
technologies
> 250 professionals from
Institutes for energy
transition and technological
research (members of FIT
association) meet in Lille
for their annual forum.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents15
NOVEMBER 2019
Carac conference
> Carac 2019 is an international conference
on the characterization of materials and
components for industry. Organized under
Nanoelec, it brings together more than
60 European experts.
© ILL
NOVEMBER 2019
European
Cybersecurity
Week
> The book “Physical security of systems -
Vulnerability of processors and operating
techniques” receives a litterary award during
the European Cybersecurity Week. Its authors
take part in Nanoelec/Pulse program.
NOVEMBER 2019
Genesis
upgrade
ontents > A gain, by a factor of 10, Table of contents
in neutron flux is obtained
from Genesis, a part of
the Nanoelec PAC-G
© CNRS
characterisation platform.
NOVEMBER 2019
International training
> RNDYNEO spreads its wings in India:
after being delivered to professsors of Amrita
Vishwa Vidyapeetham University, the training
is deployed in STMicroelectronics factories.
Table of contents IRT NANOELEC / 2020 EDITION • Highlights16
NOVEMBER 2019
SGPI visit
> IRT is visited by Guillaume Boudy,
Secretary General for Investment (SGPI)
at French government.
© CEA
DECEMBER 2019
ANR forum
> At the ANR forum in Paris, the Nanoelec
booth is visited by Guillaume Boudy,
Secretary General for investment (SGPI),
Thierry Damerval, Director-General of the
French National Agency for Scientific Research
(ANR) and Olivier Ginez, Advisor to the French
Ministry of Research and Higher Education.
© IRT Nanoelec
JANUARY 2020
Sustainable
Electronics
> First “Sustainable
Electronics” module rolled
out with experts from
STMicroelectronics, CEA and
UGA to 40 master’s students.
FEBRUARY 2020
Photonics
process flow
> New developments of the CEA-Leti silicon
photonic process flow developed as part of
Nanoelec, presented at Photonics West (USA).
It now includes integration of two layers
of optical waveguides and automated design
of advanced applications.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents17
MARCH 2020
Lithium
battery for
aeronautics
> Limatech, a start-up
© phaisarnwong2517 - Fotolia.com
that has benefited from the
support of Nanoelec/Easy-
Tech, raises e2 million for
the development of its lithium
CEA020276
batteries for aeronautics.
MARCH 2020
From technology
to design
> International webinar “From Technology to
Design” is organized by Nanoelec at the occa-
sion of DATE 2020 international conference.
3D Integration, Powergan and Photonics at a
glance are provided online.
APRIL 2020
MIT Global Startup
Workshop 2020
> Lancey Energy Storage, a start-up that
has received Nanoelec/EasyTech support,
ranks second in the “Sustainable Society
Startup Challenge” of the MIT Global Startup
Workshop 2020.
MAY 2020
Lynred joins Nanoelec
> Lynred IR detectors are key components
of many top brands in commercial thermal
imaging equipment sold across Europe,
© Lancey
Asia and North America. Lynred joins
the Nanoelec consortium in May 2020.
Table of contents IRT NANOELEC / 2020 EDITION • Highlights18
3D
Integration
SÉVERINE CHERAMY
Director of Nanoelec 3D Integration program
Look & outlook
With the advent of Industry 4.0 and the era
of connectivity, electronic devices use an ever
increasing number of components. At a time
when Moore’s Law is running out of steam,
3D integration represents an alternative for
further developing multifunction chips while
reducing overall dimensions. These 3D tech-
niques increase performance (for example,
the bandwidth between a processor and the
memory), reduce electrical consumption by
replacing a long horizontal connection with
a short vertical connection, lower production
costs by using technology adapted to the de-
sired functionality, and reduce the form factor.
These advantages are of great interest to
both academic research groups and the mi-
croelectronics industry. In addition, the rapid
emergence of this technology in the industry
requires a global approach that takes into ac-
count both the development of the technolo-
gy and the design of new 3D circuit architec-
tures, as well as the development of design,
testing and reliability tools. For these reasons,
3D integration is a natural part of Nanoelec’s
core programs.
>
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents19
Through the use of 3D electronics, it has be- To mention only certain major advances:
come possible to transfer processing func- since the start of the program in 2012, we have
tions with high added value, such as object produced two world-class proofs of concept:
recognition or motion capture. On a mobile a 3D-integrated image sensor with a connec-
system, such as a cell phone, the challenge is tion pitch of 1.4 µm; and an active interpo-
to relieve the central processor of computing ser incorporating power supply and power
capacity, energy consumption and heat dissi- management functions. Both have received
pation. This is how Nanoelec 3D Integration high-profile scientific recognition, with publi-
program has gradually shifted towards deve- cations in IEEE IEDM and IEEE ISSCC.
loping technologies for capturing and inter-
preting images, with more autonomous and Another success story of the program is the
smarter components in mind, while incorpo- introduction of a new equipment on the mar-
rating ever more complex image processing ket by the equipment manufacturer SET. This
functions. equipment, apart from being an important
event for the company with less than 100 em-
Another field of application addressed by the ployees, is also a major advance for microelec-
partners of the 3D program is high-perfor- tronics. In fact, it is the first equipment of its
mance computing, an area for which 3D inte- kind in the world.
gration and advanced packaging technologies
have gradually become the norm, due to the The success of a project is also measured by
increasing need for performance. Silicon inter- its appeal. Started with three partners in 2012,
posers, first passive and then active, i.e., smart, the 3D program had grown to six partners at
are now widely deployed in high-performance the end of 2019. Prophesee, a French start-up
systems. The 3D program has been a pioneer specializing in event-based image sensors,
in this area with the development of smart in- and Aledia, specializing in displays, joined
terposers. This was demonstrated in 2019 by the consortium in mid-2019. In 2020, Lynred,
a number of significant advances reported in global leader in designing and manufactu-
the scientific publications presented below. ring IR imaging technologies, also joined the
consortium. On the one hand, they are proof
These publications also open up vast scienti- of the relevance of the consortium’s choices
fic and technological fields that will need to with respect to 3D technologies for image
be explored to enable manufacturers to incor- capture and, on the other hand, of the generic
porate 3D architectures into their processes nature of the technological building blocks to
and products. Many questions arise especial- explore new applications that can create high
ly with respect to interfaces, such as mastery added value for new French start-ups.
of hybrid bonding, conductive channels (vias)
or even interposers.
Table of contents IRT NANOELEC / 2020 EDITION • 3D Integration20
Zoom
> New
members
at Nanoelec
> Mobilizing a global
ecosystem for reliable and Lynred, Aledia and Prophesee
join the Nanoelec consortium.
profitable 3D products Aledia is developing LED (Light-
Emitting Diode) technologies
for displays based on a unique
3D nanowire architecture.
Nearly 60 people took part in members of Nanoelec’s 3D pro- The technology enables high
the sixth 3DVLSI workshop, gram–as well as zGlue, LAM image quality and exceptional
on October 15, 2019, on the Research and Applied Mate- brightness, for both indoor
sidelines of the IEEE 2019 S3S rials. “Since the first 3DVLSI or outdoor use, with very low
conference (in San José, USA). workshop held in San Diego in consumption. “Aledia joined the
2014, we have benefited from Nanoelec/3D Integration pro-
Organized by CEA-Leti, IRT contributions from Qualcomm, gram in 2019, opening up a new
Nanoelec and Qualcomm, the Applied Materials, ARM, Atren- field of application for 3D inte-
workshop focused on high-den- ta, Cadence, CEA-Leti, Geor- gration by direct plate-to-plate
sity 3D-IC and CoolCube tech- giaTech, Global Foundries, HPE, bonding. Linking LEDs to 3D
nologies. “We have been wor- Intel, Mentor Graphics, TSMC nanowires, the heterogeneous
king on building a complete and many others”, said Séverine integration offered by bonding
ecosystem that goes from de- Cheramy. • will allow us to continue the de-
sign technology to production“, velopment of our technology”,
explained Séverine Cheramy explained Xavier Hugon, mana-
(CEA-Leti), director of the 3D ging director of Aledia, which is
program at IRT Nanoelec, who targeting the connected watch,
opened the working session. telephone, television as well as
“Over the course of six events, augmented and virtual reality
this workshop has become a fo- markets.
rum to foster the sharing of ex-
perience and know-how within “The Prophesee sensors conti-
this ecosystem. The goal is to nuously collect essential visual
bring out technologies using 3D motion information in the sce-
architectures that are truly in- ne, pixel by pixel, as do our re-
dustrially viable for reliable and tinal photosensitive cells”, said
profitable products”, she added. Prophesee president, Luca Verre.
The startup, which raised e25
Scientists and engineers from million at the end of 2019, is deve-
various key players in the loping a new category of bio-ins-
field also gave presentations: pired artificial vision systems
using patented artificial intelli-
© CEA
CEA-Leti, STMicroelectronics,
EVG, SET, Mentor Graphics–all gence sensors and algorithms.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents21
Prophesee imaging sensor for visual
motion information collection.
© Propheseee
A Lynred sensor for IR imaging. © Lynred
A Lynred sensor for IR imaging © Lynred
Aledia’s nanowire-based LEDs for display. © Aledia
© Aledia
“Through Nanoelec, we’re going leader in designing and manu- vances in this area will enable
to integrate hybrid plate-to- facturing high quality infrared Lynred to integrate new func-
plate bonding with a low inter- technologies for aerospace, tions at the level of the pixel,
connection pitch (‹5 µm) to deve- defense and commercial mar- while producing even smaller,
lop future generations of vision kets. Lynred joined the Nanoelec lighter IR devices”, said David
sensors”, explained Luca Verre. consortium in May 2020. Billon-Lanfrey, Chief Strategy
Lynred infrared detectors are “3D stacking technology will Officer of Lynred. “We are in-
key components of many top contribute to address the major terested making progress on
brands in commercial thermal development trend in IR detec- the path of smart imagers and
imaging equipment sold across tors: shrinking the pixel pitch, we think the multipartenarial
Europe, Asia and North Ame- an important parameter for in- projects of Nanoelec is a fitted
rica. The company is a global creased image resolution. Ad- frame to do it”. •
Table of contents IRT NANOELEC / 2020 EDITION • 3D Integration22
Industrializing rapid and precise
chip-to-plate bonding in production streams
In September 2019, SET
chose the Semicon Taiwan
trade fair to showcase its
latest production equip-
ment, NEO HB, developed in
partnership with Nanoelec.
The machine produces chip-to-
plate assemblies by hybrid/di-
rect bonding. The main technical
features are high precision after
assembly, high throughput, pro-
cessing of several hundred chips
per hour, and a very low level of
added defects compatible with
direct bonding. These features
make it possible to accommo-
date production markets where
the interconnection pitches are inside the CEA-Leti cleanrooms world, it is a recognized leader
very small, less than 10 μm. since 2017, and its gradual qua- in the market for high-precision
Applications such as high-per- lification have led to several pu- flip-chip bonders.
formance computing or even blications in major conferences
in the field, which has led to “Nanoelec represents a very
memory stacking can be carried
increased visibility for SET. “In stimulating multicultural ope-
out using NEO HB.
fact, the opportunities to publish ning for us”, explained Pascal
“Being in a consortium within scientific articles with academic Metzger, who also pointed out
IRT Nanoelec enables us, right teams has strengthened our that the scheme of the IRTs
from the R&D phase, to adapt credibility and our visibility in had greatly contributed to the
the design if necessary and to the inherently very narrow and realization of the SET produc-
qualify our machines by having demanding microelectronics tion machine project. “We are
access to real components and equipment market”, he added. continuing our work within
industrial production challen- Nanoelec to characterize poten-
ges. The work and discussions The company, from the tial markets for NEO HB–in par-
within the IRT provide us with Haute-Savoie region in France, ticular the production of electro-
an end-user vision for our was set up in 1975 and has the nic components for memory and
machines”, explained SET pre- specificity of being a worker coo- intensive computing - but also to
sident, Pascal Metzger. perative since 2012, following a strengthen our positioning within
takeover by its employees. With the more general market of pre-
The installation of a SET pro- more than 350 machines ins- cision assembly”, added the SET
totype direct bonding machine talled in cleanrooms around the president. •
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents23
Key publications
INCREASING CHIP-TO-CHIP BANDWIDTH
IN AN ACTIVE 3D INTERPOSER
Perceval Coudrain (CEA-Leti) as advanced network-on-chip
who works on 3D integration (NoC) interconnects, fast I/Os
and advanced packaging as for off-chip communication,
part of the 3D Integration embedded power management
> COUDRAIN & AL.,
program, received the ”Best and system-on-chip (SoC)
Active interposer
Paper Award” at the ECTC infrastructure”, Coudrain said. technology for chiplet-
conference (in May 2019, Las “Our paper reported on the basedadvanced 3D system
Vegas, USA) for his article titled first successful technological architectures
“Active interposer technology integration of chiplets on a fully 2019 IEEE 69th Electronic
for chiplet-based advanced processed, packaged and tested Components and Technology
3D system architectures”. active silicon interposer”. Conference (ECTC)
“An active interposer enables DOI:10.1109/
the addition of smart features The prize was officially ECTC.2019.00092
to the final 3D system, such announced in January 2020.
Table of contents IRT NANOELEC / 2020 EDITION • 3D Integration24
RELEASING HPC & BIG DATA APPLICATIONS
FOR 3D TECHNOLOGY
At the ISSCC 2020 conference, “This is a breakthrough in terms
(February 2020, San Francisco, of system-and-architecture
USA), CEA teams reported on integration, achieved all the way
a high-performance processor from the architectural design
breakthrough achieved as part down to a silicon prototype”,
of the 3D Integration program. said Pascal Vivet (CEA-Leti),
They implemented an active the lead author of the paper.
interposer as a modular and “In addition, 3D technology and
energy-efficient silicon platform associated design techniques are
that enables efficient integra- now available for implementing
tion of large-scale chiplet- large-scale computing systems,
based computing systems for thus offering a chiplet-based
high-performance computing 96-core computing architecture
(HPC) and big-data applications. for the first time.” Pascal Vivet (CEA) presenting Nanoelec results
at the ISSCC 2019. © DR
> VIVET & AL., A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer
offering 0.6 ns/mm Latency, 3 Tb/s/mm2 Inter-Chiplet Interconnects and 156 mW/mm2
@ 82% Peak-Efficiency DC-DC Converters
ISSCC (February 2020)
APPLYING 3D TECHNOLOGY
TO SMART IMAGE SENSORS
At the Date 2019 conference, based on events and spiking
teams from CEA-Leti gave an will reduce power consumption
overview of recent 3D technolo- with new detection and learning
gy solutions for image sensors processing capabilities. By
developed as part of the displaying our recent 3D image > VIVET & AL., Advanced
3D Technologies and
Nanoelec 3D Integration pro- sensors, we have demonstrated
Architectures for 3D
gram, including hybrid bonding the capability of 3D technology
Smart Image Sensors
technology and the Monolithic to implement fine grain pixel Design, Automation & Test
3D CoolCube™ technology, acquisition and processing in Europe Conference &
which have 3D interconnect with ultra-high speed image Exhibition (DATE),
pitches in the order of 1 μm acquisition and tile-based March 2019
and 100 nm, respectively. processing”, Pascal Vivet DOI:10.23919/
“Multi-layer 3D image sensors (CEA-Leti) explained. DATE.2019.8714886
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents25
Result of the stacking trials
using simple bonding pad wafers.
© CEA
SHAPING 3D TECHNOLOGY FOR 300 MM WAFER PROCESSES
Die-To-Wafer (D2W) direct hy- connections for the assessment can be thinned down to 10 µm
brid bonding is seen as a major of the electrical performance. without any damage. Electrical
breakthrough for the future “In a dedicated 300 mm elec- yield measured on daisy-chains
of 3D components; however, trical test vehicle and robust with more than 20,000 connec-
its industrialization raises stacking system, stackings with tions showed a yield of more
additional challenges compared a +/- 1.5 µm alignment accuracy than 75% and very limited drift
to Wafer-To-Wafer processing. and excellent bonding interface following preliminary environ-
As part of the 3D Integration were obtained (80% bonding mental reliability tests”.
program, a complete 300 mm yield)”, explained Amandine
wafer solution was developed Jouve, first author of a paper These results confirmed the
by CEA-Leti and SET to improve presenting the study at the 3DIC significant industrial potential
the bonding yield of D2W hybrid conference in Japan. “After of D2W hybrid bonding
bonding using copper inter- stacking and annealing, the die technology.
> JOUVE ET AL., Die to Wafer Direct Hybrid Bonding Demonstration
with High Alignment Accuracy and Electrical Yields
International 3D Systems Integration Conference (3DIC), October 2019
Table of contents IRT NANOELEC / 2020 EDITION • 3D Integration26
CHARACTERIZING ELECTROMIGRATION-INDUCED
DEGRADATION IN 3D COMPONENTS
As part of Nanoelec, hybrid bon-
ding-based test structures have
been characterized for further
development of backside-illu-
minated CMOS image sensors.
Scientists from CEA-Leti, ST-
Microlectronics and ESRF used
synchrotron radiation tomogra-
phy to demonstrate proportio-
nality between electromigration
(EM) induced void volumes and
time-to-failure related to vias View of the vacuum chamber of ESRF’s ID16A tomograph, on which characterisation
of the hybrid bonding was carried out on test structures. © Cloetens/ESRF
redundancy and the microstruc-
ture. “We observed a conven-
tional failure by voiding BEOL circuits, the EM phenomenon > MOREAU ET AL.,
had already been considered Correlation between
metal levels, but not hybrid
as critical for the future of the Electromigration-Related
bonding metal levels. Process
microelectronics market. void volumes and time-to-
induced bonding voids have no failure by high resolution
impact on the robustness of “More recently, hybrid bon-
X-ray tomography and
the analyzed samples. These ding processes have reached
modeling
results confirm that this type of a mass-production maturity, IEEE Electron Device Letters
hybrid bonding stack is immune but the aggressive scaling of (Volume: 40, Issue: 11),
to electromigration”, explained interconnect dimensions and November 2019
Stephane Moreau (CEA-Leti). ever increasing current den- DOI: 10.1109/
sities means that EM-induced LED.2019.2945089
In the 1960s, soon after the de- degradation remains a topic of
velopment of the first integrated interest”, Moreau explained.
APPLYING 3D TECHNOLOGY
TO SMART IMAGE SENSORS
Scientific and technological work are complementary for the com-
undertaken as part of Nanoelec plex 3D architectures required
has indicated the possibility of for the next generation of image
producing more complex image sensors. “3D Sequential archi-
systems with three levels of sta- tecture may save up to 40-60%
cked images, for capturing light of the area on dies compared to > J. MICHAILOS,
to deep processing (date proces- 2D”, explained Jean Michailos. Innovative Fine Pitch
sing, AI, VR/AR and memory). Architectures dedicated
At the Advanced SiP Technology “Sequential stacking and hybrid to Image Sensors: from
conference (USA, June 25-27, bonding provide more scalable Hybrid Bonding to 3D
2019), Jean Michailos, senior solutions compared with direct Sequential integration
program manager at STMicro- or hybrid bonding, which is invited paper, Advanced SiP
electronics, demonstrated how currently used, but such a com- Technology conference in
parallel hybrid bonding com- plex stack still requires further June 2019
bined with sequential stacking development”, he added.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents27
Theses defended in 2019
Reducing Testing and characterizing
interconnection high-density
pitches 3D interconnections
The creation of new 3D architectures requires a tho- The development of 3D technology brings about
rough understanding of the effects linked to the densi- high interconnection densities (pitches in the range
fication of interconnections and to technological pro- of µm), which is promising in terms of performance
cesses, particularly plate-to-plate assembly processes. gains. While the prior art is between 5 and 10 µm,
Among the existing techniques, direct hybrid bon- such architectures at densities in the order of micro-
ding Cu-SiO2 offers excellent robustness and a den- meters require the characterisation of technologies
sity in the order of 106 interconnections/cm2 for a pit- and the testing of application circuits that are usually
ch of 10µm. Switching to an interconnection pitch of well separated.
1.44 µm would mean this density could be multi- Imed Jani has developed test vehicles to intricately
plied by 50. As part of his thesis, Joris Jourdon stu- characterize hybrid bonding technologies, in particu-
died direct Cu-SiO2 hybrid bonding, using electrical lar the alignment of wafers and/or dies. The structure
measurements and aging tests on test vehicles with allows for characterisation of the alignment due to a
various interconnection pitches. An advanced mor- certain number of defects, in order to optimize the
phological characterisation of the bonding pads of technological process. This structure also enables
different sizes has enabled a correlation between the measurements of the electrical characteristics (R, L, C)
integration robustness and the interconnection pitch of the 3D interconnections. Lastly, this same structure
to be established. is also used to characterize 3D interconnections in an
For example, variants of bonding annealing and passi- application circuit connected with its test infrastruc-
vation have been tested in order to lower the thermal ture.
budget of bonding annealing and guaranteeing the The testing of application circuits uses standard tech-
compatibility of the “hybrid bonding” technological niques based on BIST (Built-In-Self-Test), SCAN and
brick with the entire integration. Joris Jourdon also JTAG structures, which enables dies to be sorted after
demonstrated that direct bonding was insensitive to production. The work as a whole has led to numerous
aging by electromigration up to a bonding pitch of publications and to a joint development between the
1.44 µm. CEA and STMicroelectronics.
Bonding pitch of 1,44µm developped during Joris Jourdon’s PhD. © CEA After the thesis defense by Imed Jani. © DR
JORIS JOURDON IMED JANI
3D integration by hybrid bonding: Challenges Testing and characterisation of high-density
of interconnection pitch shrinkage 3D interconnections
Thesis defended on November 19, 2019, Thesis defended on November 28, 2019, at The
at the University of Bordeaux, in partnership Université Grenoble Alpes, as part of the electronic,
with the Laboratoire de l’Intégration du Matériau electrotechnical, automatic, signal processing
au Système (Talence, Gironde). doctoral school and in partnership with CEA-Leti.
Table of contents IRT NANOELEC / 2020 EDITION • 3D Integration28
Silicon
photonics
Beyond datacoms, new applications are emer-
ging to exploit silicon photonics technology.
This is particularly true in the field of optical
sensors for automotive and transportation,
industrial and medical applications, urban
planning and environment and, of course,
for general public activities. While the advan-
tages of optical sensors are well known (selec-
tivity, speed, precision etc.), silicon photonics
enables them to be radically miniaturized to
allow widespread deployment. Indeed, silicon
CHRISTOPHE KOPP
photonics makes it possible to integrate thou-
sands of optical functions on the same chip,
Director of the thus reducing the cost of the final system (sim-
Nanoelec Silicon plified assembly, reduced electrical consump-
Photonics program tion, and decreased size/weight of products).
In this new context, light can be used for three
very different functions, such as scanning a
Look & outlook scene by an embedded Lidar, converting a
detection signal with a miniature optical
Silicon photonics is a key technology to sup- gyroscope, or analyzing data with a neuro-
port the growth of the Internet network, by morphic processor. Thus, following requests
ensuring increasingly dense and rapid digital by our industrial partners, we are supporting
data transfers over optical fiber. The Internet the emergence of these applications by deve-
now connects billions of users, but also tens loping our silicon photonics technology. Our
of billions of connected and interactive sys- technology today benefits from major tech-
tems and objects in real time. Today, the op- nological assets such as ultra low-loss silicon
tical transceivers sector in the datacoms field guides, superimposed level of silicon nitride
represents the largest share of the market for guides and laser integration. In addition, it
this technology. Supply chains have been set also offers a whole library of mature compo-
up from suppliers of substrates, design compa- nents and a design environment capable of
nies, silicon foundries, equipment, to operators. managing these new complex circuits.
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents29
Zoom
Scintil Photonique’s light-electronic
connectors will be compact and
deliver unprecedented data throughput
performance across several wavelengths.
© CEA/D. Morel
> High speeds
for data centers
Launched in 2018, the start- tens of thousands of servers. con, the transfer of certain tech-
up Scintil Photonics, which This growing market is increa- nological building blocks to a
embeds technologies de- singly turning towards inte- production foundry and support
veloped as part of the Na- grated photonics solutions due for design and testing.
noelec Silicon Photonics to the increase in transported
program, raised e4 million throughputs (near electro- The integration on silicon deve-
during a first round of fun- nic-optical integration, multi- loped in the program is the core
ding in September 2019. plexing of several wavelengths) of the startup’s technology. This
and increased volumes asso- integration enables the creation
Scintil Photonics develops si- ciated with more competitive of an externally modulated laser
licon photonics circuits that price expectations (historical whose expected performance is
incorporates all the elements technologies that required ma- state of art and uses a process
necessary for the transmission nual assembly of parts are no with low production costs. 2019
and reception of data at very longer sufficient). saw the creation of the first de-
high speeds. The first products monstrators, currently being
will support up to 800 Gb/s and Nanoelec assisted the start-up tested, as well as the prepara-
will target the market of fiber in the production of III-V/Si inte- tion of several building blocks
communications networks for grated circuit prototypes based of the design and manufacturing
storage or computing centers, on technological building blocks process. •
which are large users of op- such as wafer bonding, the pro-
tical transmitters to connect duction of the III-V part on sili-
Table of contents IRT NANOELEC
IRT NANOELEC 2019 • Silicon photonics
/ 2020 EDITION30
A step forward for silicon
photonics technology
The latest developments of SiN– with active components
the CEA-Leti silicon photo- (modulators, photodiodes and
nics process flow (produc- III-V laser sources).
tion & integration) under
Nanoelec were presented at Furthermore, with the imple-
> World the Photonic West (Februa- mentation of Mentor Graphic’s
Lightsuite Photonics compiler, it
first for
ry 4-6, 2020, San Francisco,
USA) and Optical Fiber Com- is now possible to automate the
photonics at munication (March 10-12, placement and routing opera-
2020 San Francisco, USA) tions of thousands of individual
an industrial conferences. components in order to design
advanced applications such as
scale Specifically, a process was de-
veloped to integrate two layers
high-speed interconnections,
Lidar and neuromorphic com-
of optical waveguides –Si and puting. •
Thanks to mask characteri-
sation campaigns, Daphne/
Pic50 technology was vali-
dated in 2019 by the com-
plete integration of active
silicon components (mo-
dulator and photodiodes),
passive components (wave-
guide, multiplexer, network
couplers) with silicon ni-
tride.
This is a world first on 300 mm
wafers. It position Nanoelec at
the state of the art in the pho-
tonics field. This platform is
currently used for the manufac-
ture of the Acturus mask which
carries the contributions of Lot
3 (gyroscope and Lidar circuits).
(Read bellow the summary of
the paper: “Silicon photonics
technology for 400 Gbits/s appli- SEM image of a Mach Zehnder modulator. © CEA
cations”). •
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents31
Key publications
UNPRECEDENTED RESULT ON LOSSES
IN SILICON WAVEGUIDES
Developments of low-loss We achieved record-low losses
silicon guides, achieved in at 1310 nm with 0.1 dB/cm for
recent years on an explora- single mode waveguides, with
tory basis by the CNRS-LTM the performance of the other
teams as part of the Nanoelec/ devices of the process being
Photonics program, have been preserved”, explained Quen-
successfully transferred to the tin Wilmart (CEA-Leti) who
CEA-Leti photonics process presented this result with his
flow. This enables to produce CNRS-LTM colleagues at IEEE
waveguides that achieve Group IV Photonics (August
> Q. WILMART ET AL.
unprecedented loss. 2019, Singapore). “The annea- Ultra low-loss silicon
ling step can be introduced into waveguides for 200 mm
“We applied a smoothing the production process of the photonics platform
annealing to the waveguide 200 mm photonics structures GFP, 2019
that results in practically no without any degradation in the DOI: 10.1109/
morphological deformation. complex devices”, he specified. GROUP4.2019.8925610
Table of contents IRT NANOELEC / 2020 EDITION • Silicon photonics32
LOW-LOSS WAVEGUIDES FOR NONLINEAR AND QUANTUM APPLICATIONS
At the Photonics West Confe- hired by Soitec. “In both cases, optical attenuation coefficient
rence (January 2019, USA), ultra low-loss optical wave- of the lightwave propagation
a team from CEA-Leti, Gre- guides are required to obtain ef- down to an unprecedented
noble-Alpes University, CNRS- ficient nonlinear sources along record-low value for single-
LTM (acting together under the with the photonics circuitry mode high-confinement strip
Nanoelec Photonics program) needed for quantum applica- waveguides in the C-band at
and the Ecole Centrale de tions”, he explained. 1,550 nm”.
Lyon presented technological The collaboration reported on
advances on the production of at Photonics West regarding the In terms of SiN photonics, N-H
low-loss Si and SiN waveguides production and testing of both bond overtone absorption losses
for nonlinear and quantum SiN and Si waveguides featuring in the film is the limiting factor
optics applications. record-low loss values that can for achieving low losses. “We
be used as technology building developed a tailored SiN depo-
“Silicon-on-insulator (SOI) blocks for low power consump- sition method, which controls
technology is an interesting tion optical frequency comb tensile strain and minimizes
application for on-chip en- sources and more efficient en- the hydrogen content in the
tangled photon pair sources tangled photon pairs generated deposited film. Such a film
that can be used for quantum on a chip, respectively. provides the devices with the
cryptography and computing, right specification to underpin
while SiN-on-insulator (SiNOI) In sub-micrometric Si wave- Kerr frequency combs”,
technology is promising for guides, scattering losses are Sciancalepore explained
high-power photonics as well as the primary source of optical before adding that “more
for generating Kerr frequency propagation losses. “We intro- recent results combining this
combs with several target duced a high temperature H2 film deposition technology
applications in sight, such as annealing treatment in the Si with cutting-edge etching and
atomic clocks, on-chip spec- waveguide production process annealing treatments resulted
troscopy, and terabit coherent to reduce the silicon waveguide in ultra low-loss lightwave pro-
communications”, explained sidewall roughness down to the pagation in tightly confined SiN
Corrado Sciancalepore, atomic scale”, Corrado Scian- waveguides, with record-low
who directed two PhDs on calepore explained. ”In this way, attenuation coefficients down
the collaboration before being we obtained a reduction of the to a few dB of loss per meter.”
> C. BELLEGARDE ET AL.
Technological advances on
Si and Si3N4 low-losses
waveguide platforms for
nonlinear and quantum optics
applications
Proc. SPIE OPTO 10933,
Advances in Photonics of
Quantum Computing, Memory,
and Communication XII,
1093309 (2019)
Doi: 10.1117/12.2508617
a) Tilted SEM cross section images of the STRIP waveguide profiles after a) standard and b) optimized H2 annealing;
c) Line edge roughness measured by AFM along the STRIP sidewalls after the standard and optimized H2 annealing
treatment. © DR
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents33
GERMANIUM FOR PHOTODETECTORS AND LASERS
Work on the establishment of GeSn contacts. In particular,
CMOS ohmic contacts compa- the addition of Pt or Co to
tible with Germanium-Tin alloys modify the properties of
(under Nanoelec/Photonics Ni-based contacts and their
program) received the “Best ar- thermal stability was discussed
ticle” award at the International during the presentation.
Workshop on Junction Techno-
logy (IWJT, June 2019, Japan). “We have shown that the
“This award is for the tremen- addition of an alloy element,
dous work done by Andrea Pt in particular, can significantly
Quintero (CEA Leti) in particular improve the thermal stability
during his thesis”, said Philippe of the contacts. This is a
Rodriguez (CEA Leti), project crucial technological barrier
manager for Nanoelec. “Our for GeSn-based devices”,
work identifies possible ways to explained Andrea Quintero,
make contacts for future active first author of the paper
silicon components such as ul- (Quintero2019, Quintero2020).
tra-sensitive photo-detectors or
even Germanium-based lasers”. Mr. Rodriguez’s team had
already received an award (the
The collaboration, made up best student article) at this
of researchers from same conference, in 2015, for
CEA-Leti, CNRS, Grenoble Alpes its results on CMOS compatible
Best Paper Award of IWJT-2019 award ceremony:
Philippe Rodriguez (CEA Leti) and Satoshi Shibata and Paris-Saclay universities, contacts on III-V materials,
(Program Chair). © Frédéric Mazen (CEA Leti)
gave a presentation in Japan on results that have been success-
the physico-chemical properties fully implemented for hybrid
of Ni-based alloys for making lasers (Szelag2017, Szelag2019).
> B. SZELAG ET AL.
Hybrid III-V/Si DFB laser integration on a 200 mm fully CMOS-compatible silicon photonics platform
2017 IEEE International Electron Devices Meeting (IEDM 2017), 24.1
> B. SZELAG ET AL.
Hybrid III-V/Silicon technology for laser integration on a 200 mm fully CMOS-compatible silicon
photonics platform
IEEE J. Select. Topics Quantum Electron. 25, 8201210 (2019)
> A. QUINTERO ET AL.
Effects of alloying elements (Pt or Co) on nickel-based contact technology for GeSn layers
19th International Workshop on Junction Technology (IWJT-2019)
> A. QUINTERO ET AL.
Impact of alloying elements (Co, Pt) on nickel stanogermanide formation
Mater. Sci. Semicond Process. 108, 104890 (2020)
Table of contents IRT NANOELEC / 2020 EDITION • Silicon photonics34
SILICON PHOTONICS TECHNOLOGY
FOR 400 GBITS/S APPLICATIONS
To cope with the increasing has been achieved due to the
data traffic of large computing integration of a supplementary
centers, silicon photonics tech- SiN waveguide layer that enables
nology has provided a data rate wideband optical coupling. This
up to 100 Gbit/s per connector technology also has a strong
Experimental setup for on wafer O/E measurements:
for a few years. As a next step, potential for new devices, not electrical probe and TIA card on the left, and optical
a research team from STMi- only for actual Si-photonics fiber array and piezo positioner on the right. © DR
croelectronics and University di applications but also for new
Pavia demonstrated, during the contexts, such as automotive > F. BOEUF ET AL.
IEEE International Electron De- sensors”, said Frédéric Boeuf A Silicon Photonics
Technology for 400Gbits/s
vices Meeting (IEDM, December (STMicroelectronics), first
applications
2019, USA), a Si-photonics tech- author of the study carried out
2019 IEEE International
nology suitable for 400 Gbit/s as part of Nanoelec. Electron Devices Meeting
400G-DR4 standard operations1. 1
FR4 and DR4 are standards for data transmission in (IEDM), paper # 33.1
“Moreover, the extension of our data centers: DR4 (Direct Reach) involves distances
between 500 m and 2 km whereas FR4 (Far Reach) DOI: 10.1109/
technology towards 400G-FR4 involves distances up to 10 km and stipulates the use
of four distinct wavelengths on the same fiber. IEDM19573.2019.8993627
LASER INTEGRATION ON A 200-MM FULLY CMOS-COMPATIBLE
SILICON PHOTONICS PROCESS
In the Journal of Selected for low-cost production devices. Collective III-V die
Topics in Quantum Electronics, process in the future”. bonding is proposed for this
Bertrand Szelag (CEA-Leti) et III-V material is incorporated on technology.
al. presented a hybrid III-V/Si top of a mature silicon photo- “This new technology offers
photonics process they de- nics front-end wafer through the opportunity to design
veloped at CEA-Leti, as part direct molecular bonding, which photonics circuits with
of the Nanoelec/Photonics enables the monolithic integra- monolithically integrated
program. Szelag explained that tion of light sources. Distributed lasers on large size SOI wafers
“the overall integration of the Feedback Laser Diode (DFB) and provides convergence of
hybrid laser is completed in a and Distributed Bragg Reflector silicon-based and InP-based
fully CMOS-compatible process, laser reference designs are technologies, which offers the
and leverages the large scale used as test vehicles for the advantages of each material.
integration capabilities of silicon process validation. A modular This convergence enables
photonics. “It is compatible approach is used in order to various applications with
with 200 mm technology and minimize the impact on the a unified technology”,
scalable to 300mm wafers already qualified silicon-based said Szelag.
> B. SZELAG ET AL. HYBRID III-V
Silicon Technology for Laser Integration on a 200-mm Fully CMOS-Compatible Silicon Photonics Platform
IEEE Journal of Selected Topics in Quantum Electronics
IRT NANOELEC / 2020 EDITION • Scientific & technical highlights Table of contents35
Thesis defended in 2019
Integrated photonics circuits in silicon nitride for non-linear optics
Houssein El Dirani’s thesis deals with the exponential co-integration with other optoelectronic devices on
rise in data traffic linked to developments in online the same chip.
connections between objects and people. This growth “In particular, we developed a production process for
in data transmission rates calls for new technologies Si3N4 films with a thickness of 740 nm, without the use
such as optical frequency combs that have revolutio- of annealing and with good control of the constraints
nized the telecommunications sector over the past typically associated with this type of material for
decade. The concept of optical frequency combs also non-linear optics, explained Houssein El Dirani. This
finds applications in optical detection, chemical detec- new approach has also allowed us to demonstrate
tion and optical clocks. sources of frequency combs incorporated on a chip
Houssein El Dirani focused on the design, manufac- using silicon nitride resonators coupled by abutment to
ture and characterisation of non-linear silicon nitride a III-V DFB laser used as a pump. This proof of concept
photonics circuits without annealing, compatible with validates our process for non-linear photonics circuits
CMOS technology, and standard in the electronics in- in Si3N4 for ultra-compact and low-consumption opti-
dustry thereby enabling low cost manufacturing and cal frequency combs”.
HOUSSEIN EL DIRANI
Development of high quality silicon nitride chips for integrated non-linear photonics
Thesis defended on October 7, 2019, at the Ecole Centrale de Lyon in partnership with the Lyon Institute
for Nanotechnologies.
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