EBU External Bus Unit - AURIX Microcontroller Training V1.0 2019-03 - Infineon Technologies
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EBU
External Bus Unit
AURIX™ Microcontroller Training
V1.0 2019-03
Please read the Important Notice and Warnings at the end of this documentEBU
External Bus Unit
Address/ Data Bus External Bus Unit (EBU) Highlights
Kernel SRI I/F
›
Address Bus
SRI Bus Allows to connect high variety of external
SRAM Control Matrix
memories
Burst Flash Control
› Highly programmable access parameters
SDRAM Control Clock
Control
for extended configuration capabilities to
Chip Select Lines configure Bus components (Burst Flash,
synchronous & asynchronous SRAM,
NAND Flash, FPGA…)
Key Features Customer Benefits
Burst FLASH support › Extend the NVM capabilities for large
SW Projects (code and constants)
Synchronous SRAM support › Extend the VM capabilities for large SW
Projects (data)
Highly programmable access parameters › Wide variety of external memories can
be supported
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 2EBU Burst FLASH support The Memory Controller is designed to generate waveforms compatible with the access modes of: › INTEL and compatible burst flash devices › SPANSION and compatible burst flash devices › Samsung OneNAND™ burst capable NAND flash and compatible devices › M-Systems DiskOnchipG3 and compatible devices 2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 3
EBU Synchronous SRAM support The Memory Controller is designed to generate waveforms compatible with the asynchronous/synchronous modes of: › Standard asynchronous SRAM › Standard synchronous SRAM › INFINEON and MICRON cellular RAM › Fujitsu and compatible FCRAM™/uTRAM™/CosmoRAM › SSRAM from e.g. GSI/ISSI/IDT 2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 4
EBU Highly programmable access parameters › Fully synchronous/asynchronous timing with flexible programmable timing parameters (address cycles, read wait cycles, data cycles). This allows optimized control waveforms to be generated for controlling accesses to the attached memory devices › Programmable WAIT function, which allows support of memory devices with a variable access latency › Programmable burst (mode and length) › 8-bit/16-bit/32-bit device width › Page mode read accesses › Resynchronization of read data to a feedback clock to maximize the frequency of operation (optional) 2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 5
EBU
System integration
› The Memory Controller module for
FPU FPU
SRI-based systems connects on- PMI TriCore DMI PMI TriCore DMI LMU
CIF
1.6P 1.6P FFT
chip controller cores (e.g.
SRI Cross Bar
TriCore™ CPU, DMA Controller) to
external resources such as PMI
FPU
TriCore DMI
DFlash PFlash PFlash
EBU
memories and peripherals 1.6P
PMU0
› Any SRI master can (in
Bridge HSSL DMA OCDS
conjunction with an SRI Matrix)
access external memories through Ports
HSM
the Memory Controller
GPT12x
CCU6x
SMU
STM
SCU
BCU
IR
GTM DS-ADCx
› A pin multiplexing scheme has VADCx
System Peripheral Bus
been implemented to allow the use
MultiCAN+
EVR
ASCLINx
Ethernet
of low power, 5 V compatible pads
FlexRay
QSPIx
PSI5S
MSCx
SENT
PSI5
FCE
IOM
I²C
5V or 3.3V
for the 32 bit data bus single supply
AURIX TC29x Block diagram
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 6Application example
Typical external memory system
Burst Flash SRAM
Memory
Interface
Data Flash Peripheral
Overview Advantages
› External Flash memory › Extend the memory capabilities for large
SW Projects (code, constants and data)
› External SRAM memory
› Multiplexed access (address & data on
the same bus)
› Data buffering (1 single write buffer to
SRI & 2 read buffers)
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 7Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-03 IMPORTANT NOTICE For further information on the product,
Published by The information given in this document shall in no technology, delivery terms and conditions and
Infineon Technologies AG event be regarded as a guarantee of conditions or prices please contact your nearest Infineon
81726 Munich, Germany characteristics (“Beschaffenheitsgarantie”) . Technologies office (www.infineon.com).
With respect to any examples, hints or any typical
© 2019 Infineon Technologies AG. WARNINGS
values stated herein and/or any information
All Rights Reserved. Due to technical requirements products may
regarding the application of the product, Infineon
contain dangerous substances. For information
Technologies hereby disclaims any and all
Do you have a question about this on the types in question please contact your
warranties and liabilities of any kind, including
document? nearest Infineon Technologies office.
without limitation warranties of non-infringement
Email: erratum@infineon.com
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Document reference In addition, any information given in this
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with its obligations stated in this document and
may not be used in any applications where a
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