STATISTICAL-BASED ANALYSIS AND DESIGN FOR VLSI ASICS AND SYSTEMS-ON-CHIP (SOCS) - IBM ENGINEERING & TECHNOLOGY SERVICES MAY 2005

Page created by Mildred Henderson
 
CONTINUE READING
IBM Engineering & Technology Services
May 2005

                                        Statistical-based analysis
                                        and design for VLSI ASICs and
                                        Systems-on-Chip (SoCs)
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 2

                                          Introduction
                    Contents              Until now, within the very large scale integration (VLSI) semiconductor industry,
                                          design-for-manufacturing (DFM) referred to any tool or technique that increases
    2   Introduction                      the functional yield or yield-learning rate of a chip. Generally, these tools or
    2   Process technologies and          techniques attempt to minimize the exposure of a design to contaminants or
        performance                       defects (for example, dust particles, or metal opens/bridges, respectively) that
    5   Statistical analysis              cause catastrophic yield loss.
    8   Manufacturing statistics
    10 Beyond statistical analysis        Starting with 90-nm process technology and going forward, parametric-limited
    11 Conclusion                         performance yield — or circuit-limited yield — has become an important factor
    11 For more information               in the design and fabrication of leading-edge chips (see Figure 1). It is this
                                          parametric-based DFM that is the subject of this paper.

                                          Process technologies and performance
                                          For Moore’s law to continue to be pragmatically valid, new process technologies
                                          must provide more than the projected increases in density and chip capacity.
                                          They also need to provide a chip-level performance – or, more recently,
                                          performance vs. power – improvement for an equivalent design. That is, if a
                                          design clocks at 500 MHz in one technology generation, that design needs to
                                          clock at a higher frequency (generally, approximately 10-20 percent higher),
                                          when mapped to the next-generation technology. Although less visible than
                                          the density component of Moore’s law, this speedup has allowed designs to
                                          be mapped to next-generation technologies without exposing the current
                                          performance specification, even in the face of lower initial yields and wider
                                          parametric variability.
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 3

                                                                          Relative performance
                  Highlights                                           (Variability shown as range)

                                                                      CMOS technology generation
   For Moore’s law to continue to be
                                          Figure 1. The importance of parametric-limited performance yield
   pragmatically valid, new process
   technologies need to be both denser
                                          For more recent process technologies, this 10-20 percent speedup has been
   and faster than previous ones
                                          increasingly difficult to achieve. Companies have been driven to new materials
                                          such as copper and low-k dielectrics, and more exotic substrates such as
                                          silicon-on-insulator (SOI) and strained silicon. Yet they continue to face major
                                          challenges in increasing chip-level performance. The actual rate of increase in
                                          chip-level performance is more representatively shown as in Figure 2.

                                                                          Relative performance
                                                                       (Variability shown as range)

                                                                      CMOS technology generation
                                          Figure 2. Chip-level performance rate
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 4

                                              Now, compound the decrease in the rate of chip-level performance improvement
                  Highlights                  with an increase in parametric process variability, and the worst-case chip-level
                                              performance from one process technology to the next can actually decrease, as
                                              shown in Figure 3.

                                                                             Relative performance
   For the vast majority of designs, some
                                                                          (Variability shown as range)
   other approach is needed, because
   most designs cannot afford either the
   team size or schedule that is typical of
   a high-volume processor design.

                                                                         CMOS technology generation

                                              Figure 3. Worst-case chip-level performance

                                              The semiconductor industry is also exploiting more aggressive sub-wavelength
                                              lithography techniques in transitioning from 90- to 65-nm process technology,
                                              which contribute to the significantly greater overall variability projected for
                                              65-nm process technology.
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 5

                                          Not all designs are as performance-sensitive at absolute worst-case process
                   Highlights             conditions. For example, processor designers can use custom physical-design
                                          techniques to increase the performance correlation and tracking of a design.
                                          This can lessen or eliminate the chance of worst-case chip-level performance.
   If designs can be analyzed, using      Further, processor chips can be performance-sorted and — depending on
   the actual statistical distributions   market demand — might all be salable at different price points. However, for
   and correlations for the different     the vast majority of designs, some other approach is necessary. Most design
   parametric variables, worst-case       projects cannot afford either the team size or schedule typical of a high-
   performance can be bounded at a        volume processor design.
   level considerably higher than the
   absolute worst-case performance.       Statistical analysis
                                          The resolution to the dilemma illustrated in Figure 3 is actually implicit in
                                          the curve. If designs can be analyzed, using the actual statistical distributions
                                          and correlations for the different parametric variables, worst-case performance
                                          can be bounded at a level considerably higher than the absolute worst-case
                                          performance, as shown in Figure 4. The performance can be bounded at some
                                          higher level, with the chances of worse performance at a negligible level (such
                                          as 1 - 2 percent of all chips processed). Even higher worst-case performance
                                          can be achieved, at the cost of a larger, but statistically manageable, fallout
                                          (such as 10 - 20 percent). Of course, this parametric yield fallout needs to be
                                          testable. The field reliability of components that pass at-speed manufacturing
                                          test cannot degrade from today’s levels.
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 6

                                                                           Relative performance
                  Highlights                                            (Variability shown as range)

   By enabling worst-case chip-level
   performance to more closely approach
   nominal-case performance, statistical
   analysis provides both a significant
   one-time performance increase at the                                CMOS technology generation
   time of its introduction, and an
                                           Figure 4. Absolute worst-case performance
   ongoing, increasing desensitivity to
   the increasing process variations of
                                           Statistical analysis can also be leveraged another way. As shown in Figure 5, it
   each future technology.
                                           can be used to provide a midlife performance boost to a current design in a
                                           current technology.

                                                                           Relative performance
                                                                        (Variability shown as range)

                                                                      CMOS technology generation

                                           Figure 5. Midlife performance boost
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 7

                                          By enabling worst-case chip-level performance to more closely approach
                 Highlights               nominal-case performance, statistical analysis provides both a significant
                                          one-time performance increase at the time of its introduction, and an
                                          ongoing, increasing desensitivity to the increasing process variations of each
                                          future technology.

                                          There is no magic here. Today’s approach to “3 sigma” worst-case analysis,
                                          which uses the limits, rather than the distribution, of process parameters is
                                          actually “3 sqrt(n) sigma” analysis, where n is the number of independent
                                          parameters. So, 10 - 25 independent parameters actually equate to “~10 - 15
                                          sigma” analysis, requiring designs to pass timing analysis for situations that
                                          have virtually no chance of occurring. Further, the 3-sigma analysis assumes
                                          the distribution of any single parameter is uniform, whereas manufacturing
                                          generally holds these parameters to tighter distributions, once a process has
                                          been centered to optimize overall yield.
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 8

                                            Manufacturing statistics
                  Highlights                With all the benefits of statistical analysis, an obvious question arises: “Why
                                            wasn’t this done earlier?” To answer this question, some of the economics of
                                            the VLSI industry need to be recalled.

   While the statistical techniques might   First, in a self-fulfilling way, Moore’s law has driven the VLSI industry to
   have been cost-effective to use — if     build and ramp up newer process technologies as fast as process tooling was
   they had existed — the economics of      production-ready, sometimes even before the current process achieved ultimate
   the electronic design and automation     yields. So long as the market outlook was sufficiently favorable, the benefits
   (EDA) industry made it too speculative   of getting a design into the newest process technology often outweighed the
   to develop these tools.                  lower initial yields and lessened performance optimization. While the statistical
                                            techniques might have been cost-effective to use — if they had existed — the
                                            economics of the electronic design and automation (EDA) industry made it too
                                            speculative to develop these tools.

                                            Second, to exploit statistical analysis, more than new EDA tools are needed.
                                            Chip manufacturers need to gather, analyze, and make available the required
                                            parametric distributions. Their factory-floor IT systems need to be able to
                                            archive, retrieve, and analyze all types of cross-sections (e.g. by wafer, by part
                                            number, by location on wafer, by particular process tool and so on).
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 9

                                              Third, with fewer parameters and smaller variability, brute-force Monte Carlo
                   Highlights                 analysis techniques can be used to characterize the performance of all of the
                                              elements in an application-specific integrated circuit (ASIC) library, across the
                                              entire process window and operating conditions. This implicitly accounts for
                                              statistics in the performance characterization of the off-the-shelf libraries, but
                                              leaves the interconnect analysis exposed to the increased pessimism of a non-
                                              statistical approach.

                                              Finally, precursors to statistical analysis actually have been deployed by leading-
                                              edge VLSI companies. IBM has long exploited design-based correlations to
   Since its inception, IBM’s ASIC            lessen the pessimism of timing analysis. More recently, we have deployed the
   business has considered making             infrastructure statistical-based analysis of metal variations in thickness, width,
   performance and testability                and overlay.
   specifications as much a part of our
   first-time-right track record as logical   These techniques have allowed IBM to consistently maintain a greater than
   and functional correctness.                90 percent first-time-right success rate for our internal and OEM ASIC
                                              businesses. Since its inception, IBM’s ASIC business has considered the
                                              achievement of performance and testability specifications as much a part of our
                                              first-time-right track record as logical and functional correctness. As a leading-
                                              edge integrated device manufacturer (IDM), IBM is able to provide all necessary
                                              process and library modeling information available to its EDA development
                                              team. Not only has this positioned IBM at the forefront of statistical analysis, it
                                              led to earlier IBM innovations, such as our Delay Calculation Language (DCL) —
                                              a more flexible and extensible format for representing circuit and library timing
                                              (and more recently, noise and power) information than other existing library
                                              modeling formats.
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 10

                                          Beyond statistical analysis
                  Highlights              Although statistical analysis is just emerging as an EDA capability, it’s worthwhile
                                          to ask: “What lies beyond analysis”? Historically, EDA analysis and design tools
                                          have advanced in tandem, with design tools taking as input the design pinch
                                          points identified by analysis tools, and re-optimizing to eliminate them.
   Even in the near term, physical
   synthesis and routing-based-           This is likely to continue. While fixing an isolated design problem is somewhat
   optimization are going to be           separable from design analysis, designers are increasingly faced with the situation
   increasingly guided by statistical     that fixing one design problem can cause one or more additional problems
   timing analysis, and will then         elsewhere. If the design tool is not as “statistics aware” as the analysis tool, the
   evolve to explicitly optimize          iterative design closure process can diverge badly.
   robustness, as well as performance,
   area and power.                        Physical synthesis and routing-based-optimization are going to be
                                          increasingly guided by statistical timing analysis, and will evolve to explicitly
                                          optimize robustness (such as desensitivity of a design to process variability, vs.
                                          performance), as well as performance, area and power.
Statistical-based analysis and design for VLSI ASICs and Systems-on-Chip (SoCs)
Page 11

                                           Conclusion
                   Highlights              Because of the process technology challenges in moving to geometries smaller
                                           than 90 nm, and the longevity and severity of the most recent industry
                                           downturn, it may appear that the technical progress and market growth of our
   Statistical methods can go a long way
                                           industry has fundamentally slowed. Two things should be kept in mind:
   toward desensitizing designs from the
   variability of future CMOS scaling.     •   Less than twenty percent of the global market uses VLSI-based products at a
                                               “saturated” level. And even that twenty percent is on a maximum four-year
                                               replacement cycle for the consumer segment.
                                           •   Classic complementary metal oxide semiconductor (CMOS) scaling can extend to
                                               substantially smaller geometries. What currently are far from ideal are physical
                                               and electrical process variabilities, fringing effects whose range are approaching
                                               minimum feature sizes, and thermal and sub-threshold effects.
   While the fringing effects need to
   be minimized through innovative
   physical and interconnect structures,
                                           Statistical methods can go a long way toward desensitizing designs from the
   their variability can be managed,
                                           variability of future CMOS scaling. While the fringing effects may be lessened
   using statistical analysis and,
                                           through innovative physical and interconnect structures, their associated
   ultimately, statistical design tools.
                                           variability can be successfully managed using statistical analysis and ultimately,
                                           statistical design tools.

                                           For more information
                                           To learn more about statistical analysis and design, contact your IBM
                                           representative or see:

                                           ibm.com/technology
© Copyright IBM Corporation 2005

  IBM Engineering & Technology Services
  Route 100
  Somers, NY 10589
  U.S.A.

  Produced in the United States of America
  04-05
  All Rights Reserved

  IBM and the IBM logo are trademarks of International
  Business Machines Corporation in the United States,
  other countries or both.

  Other company, product and service names may be
  trademarks or service marks of others.

  All information contained in this document is subject to
  change without notice. The products described in this
  document are NOT intended for use in applications such
  as implantation, life support or other hazardous uses
  where malfunction could result in death, bodily injury or
  catastrophic property damage. The information con-
  tained in this document does not affect or change IBM
  product specifications or warranties.

  THE INFORMATION CONTAINED IN THIS DOCUMENT
  IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM
  be liable for damages arising directly or indirectly from
  any use of the information contained in this document.

  Nothing in this document shall operate as an express or
  implied license or indemnity under the intellectual prop-
  erty rights of IBM or third parties. All information contained
  in this document was obtained in specific environments,
  and is presented as an illustration. The results obtained in
  other operating environments may vary.

  References in this publication to IBM products and
  services do not imply that IBM intends to make them
  available in all countries in which IBM operates.

  The services mentioned herein are offered in Canada
  under the name IBM E&TS, a division of IBM Canada
  Ltd. and are offered elsewhere in the world by IBM
  Corporation under the name IBM Engineering &
  Technology Services.

  The examples cited in this brochure, including any
  performance/delivery achievements and any cost
  savings referenced in this brochure, are fact-specific
  and are based on past performance. They are not a
  guarantee of results and may not be representative
  of what can be achieved in other circumstances.

  The IBM home page can be found at ibm.com
You can also read