Allegro Design Authoring - Create design intent with ease for simple to complex designs
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Allegro Design Authoring
Create design intent with ease for simple to complex designs
Systems companies looking to create new products at the lowest possible cost need a way to
author their designs with ease in a shorter, more predictable design cycle. With the increased
use of new standards-based interfaces, architectures, and implementation approaches, hardware
designers require a design authoring solution that scales with their evolving technology and
methodology needs. Cadence® Allegro® Design Authoring is a scalable and easy-to-use solution
for fast design intent creation (connectivity plus high-speed constraints) using either schematics or
a spreadsheet-like interface.
Allegro Design Authoring straint sets (ECSets). This enables a Features
constraint-driven PCB implementation
Available in “base plus options” con- Schematic Editing
flow to ensure a shorter, predictable,
figurations, Allegro Design Authoring
and complete PCB design cycle from Allegro Design Authoring maximizes
provides a scalable solution that
concept to manufacturing. workflow efficiencies through its
adapts to your changing needs.
Other configurations include a Team collaborative design approach. The
Allegro Design Authoring (Base)
Design Option, an FPGA System design can be partitioned at a sheet
provides a robust, yet easy-to-use
Planner Option, an FPGA ASIC or block level, and each designer
schematic creation environment that
Prototyping Option, and a Design can be assigned one or more blocks
allows you to create flat or hierarchi-
Publisher Option. or sheets. Any number of designers
cal schematics for your products. Its
can work on different parts of the
enterprise-ready Schematic Editor
Benefits same design simultaneously without
integrates seamlessly with Allegro
interfering with each other. The vari-
AMS Simulator, Allegro PCB SI Signal
• Shortens time to create design ous design stages can then be com-
Explorer and Simulator, and Allegro
intent bined before proceeding to layout in
PCB Designer, enabling a constraint-
Allegro PCB Editor. This concurrent
driven PCB design flow for predictable • Enables concurrent schematic and
design approach makes Allegro Design
digital, analog, RF, and mixed-signal layout design
Authoring extremely productive for
designs.
• Reduces design spins via a proven, large designs. Designers work on the
The Multi-Style Option allows you to constraint-driven flow board layout and schematic in parallel.
create connectivity for your designs Changes made in either Allegro Design
• Reduces rework and prevents errors
very quickly without requiring symbols Authoring or Allegro PCB Editor
by supporting flexible design reuse
or having to graphically connect pins/ can be merged and synchronized
ports on symbols. Its spreadsheet- • Eliminates rework with a single periodically.
like interface makes it easy to cre- schematic that drives digital, analog,
Schematic Editor within Allegro Design
ate design intent for large pin-count and pre-layout signal integrity
Authoring allows you to create flat or
devices or backplane designs 5x to 20x simulators
hierarchical designs without requir-
faster than traditional schematic-based
• Reduces total cost of ownership ing you to enter into “hierarchical”
approaches. The High-Speed Option
through a scalable “base plus or “occurrence” modes. It provides a
allows you to create true design
options” configuration that is cross-referencer that annotates the
intent by integrating high-speed con-
enterprise deployment–ready schematic with references to allow
straints with the connectivity through
easy tracking of signals on plotted
hierarchical, reusable electrical con-Allegro Design Authoring
schematics. Schematic Editor also allows Design Reuse with Module Design (placement-aware pin assignment syn-
you to place multiple discrete components thesis). This unique placement-aware pin
Most designs start from other designs or
quickly. For example, to place 512 resis- assignment approach eliminates unnec-
reuse significant parts of existing designs.
tors that tie into a 512 bit bus, you need essary physical design iterations that are
Allegro Design Authoring gives you mul-
only place one resistor on the bus and inherent in manual approaches.
tiple choices for reuse, so you can select
specify that 512 such components need
the most effective approach for their FPGA System Planner reads Allegro Design
to be placed, and Schematic Editor will
design. Sheets from old designs, blocks, Authoring symbols and creates Allegro
connect 512 bits to 512, greatly reduc-
or entire designs can be reused, which Design Authoring schematics. It also
ing the number of graphical components
reduces rework and errors. You can copy integrates with Allegro PCB Editor, from
needing to be placed and displayed within
single or multiple sheets from one design which it uses existing footprint libraries
a design.
to another using the Import Sheet UI, or via a floorplan view. Should placement
The Allegro Design Authoring point-to- just copy/paste special circuitry among change during layout, pin optimiza-
point wire router makes it easy to connect different designs. You can reuse electrical tion using FPGA System Planner can be
ports on two different symbols, saving constraints as part of a block or by using accessed directly from Allegro PCB Editor.
time to create the schematics. Similarly, electrical constraint sets (ECSets). The
Design Variants
automatic insertion of a two-pin com- technology further allows you to create
ponent within an existing net generates “reuse” blocks and place them in a library By leveraging the design variants capabil-
associated input and output pins auto- for use in other designs, just as with com- ity in Allegro Design Authoring, you can
matically while adhering to the associ- ponents. The connectivity, constraints, conserve even more time and effort at the
ated net names, shortening time to create and layout from each block can also be structural level. The design variants capa-
basic schematics. reused. The same block can be used bility eliminates having to create slightly
multiple times in the same design without different versions of the same basic
Whether you’re using a flat design with
renaming or copying. design—for example, offering graduated
a few hundred sheets or a hierarchical
performance levels to different market
design with multiple levels of hierarchy, FPGA Design-In
segments, or addressing varying regional
Global Navigate allows you to navigate to
Allegro Design Authoring provides a com- requirements. It enables you to derive
any net or part in your design with a few
prehensive FPGA design-in solution. The variants of a single base design by assign-
mouse clicks. The dock-able Global Find
Build Physical Wizard allows you to import ing alternate sets of attributes to the
and Replace window allows you to find
Xilinx, Actel, and Altera FPGAs into your components, wires, or other elements of
and replace parts or properties across the
Allegro Design Authoring schematic and the design. An engineering change order
design. These can be highlighted directly
automatically creates the files required to (ECO) applied to the base design auto-
from Allegro PCB Editor or Allegro PCB SI.
drive Allegro PCB Editor, Allegro Design matically propagates to all its variants.
Customizable Rules Checking Authoring, and the digital simulation
Bill of Materials Generation
flow. Allegro Design Authoring also intelli-
Allegro Design Authoring eliminates mul-
gently manages the interface to the FPGA Allegro Design Authoring gives you fine-
tiple design iterations with Rules Checker,
so that the board schematic changes tuned control over bill of materials (BOM)
a truly comprehensive verification facil-
when the FPGA pin assignments change, creation, ensuring parts lists that meet
ity. It allows you to perform electrical
but the design does not change logically. your needs precisely and contain every-
and design rule checks to verify drafting
thing necessary for manufacturing. You
standards and correct property names, FPGA-PCB Co-Design
can generate a BOM for a base design or
syntax, and values. Rules Checker also
Integrated with Allegro Design Authoring, any of its variants, list non-electrical parts
includes rules to support downstream
Allegro FPGA System Planner provides in a callout file, and have Allegro Design
processing, fan-in and fan-out errors,
a complete, scalable solution for FPGA- Authoring merge them in the BOM with
load errors, power requirements, and cost
PCB co-design that allows you to cre- the electrical parts from the schematic.
requirements. Rules Checker checks the
ate an optimum correct-by-construction You can associate electrical and non-
alignment between logical and physical
pin assignment. FPGA pin assignment electrical parts in the schematic—for
designs. In addition, it lets you define cus-
is synthesized automatically based on example, a heatsink with an IC—and
tom rules to ensure conformity to design
user-specified, interface-based connectiv- have that association shown in the BOM.
requirements specific to your company or
ity (design intent), as well as FPGA pin You can output the BOM in ASCII text,
your projects. Rules Checker can be used
assignment rules (FPGA rules), and actual spreadsheet, or HTML format as needed
for schematics, symbols, and the physi-
placement of FPGAs on PCB (relative to optimize transmission to manufacturing
cal netlists. It has a rule development and
placement). With automatic pin assign- and other recipients.
debugging environment for defining rules
and can run in batch mode, facilitating ment synthesis, you avoid manual error-
deployment in an enterprise environment. prone processes while shortening the
time to create initial pin assignment that
accounts for FPGA placement on the PCB
www.cadence.com 2Allegro Design Authoring
PCB Editor Integration lation environments to quickly locate and while the software automatically com-
characterize design bugs. This provides a municates compliance with the engineer’s
The integration of Allegro Design
reliable, low-cost analog simulation and performance requirements.
Authoring with Allegro PCB Editor makes
verification solution for Allegro Design
it the Schematic Editor of choice for all RF Circuit Design
Authoring customers on the Windows
designers looking to increase productivity.
platform. At the other end of the spec- Many of today’s digital PCB systems
The front-to-back flow automatically takes
trum, Analog Workbench provides a include some circuitry that operates at
care of backannotation of pin, section,
high-end comprehensive analog design radio frequencies. These blocks have
and component swapping in Allegro PCB
environment that is integrated with special design requirements and are pre-
Editor to Allegro Design Authoring sche-
Allegro Design Authoring only on the dominantly designed and simulated with
matics. Two-way cross-probing between
UNIX platform. Agilent ADS (formerly Agilent EEsof).
Allegro PCB Editor and Allegro Design
However, this block needs to be pres-
Authoring allows you to locate compo- High-Speed Design
ent on the same board along with other
nents in the schematic by highlighting
Integration with Allegro Constraint digital and analog circuitry. To enable this,
the component in Allegro PCB Editor and
Manager makes creating design intent Allegro Design Authoring and Allegro PCB
vice versa.
quick and easy—it adds physical and Editor provide a flow to import RF blocks
To help in the placement phase, you can electrical constraints that make communi- designed in Agilent ADS into the Cadence
place components in Allegro PCB Editor cation of constraints reliable. Integrating board design flow.
by selecting the components in the constraints with schematic creation
Allegro PCB Editor and Allegro Design
Allegro Design Authoring schematic can- makes capturing and communicating
Authoring can automatically import
vas. You can also place all components design intent to downstream processes
the ADS physical layout and sche-
on an Allegro Design Authoring sche- very efficient and eliminates the risk of
matic through a robust interface. Once
matic page in a single step in Allegro PCB unnecessary prototype iterations. It also
imported, the ADS design behaves like
Editor. Using design differences, you can shortens the PCB implementation pro-
a module, with its components mapped
compare schematics and boards before cess by enabling a constraint-driven PCB
to Allegro PCB Editor library parts. The
transferring design information in either design flow.
imported module can be locked (to pre-
direction. With design association, you
The spreadsheet-like system allows you to vent editing) or unlocked (to allow edit-
can backannotate terminators and bypass
capture all electrical constraints within the ing). Even if locked, the module still
capacitors added directly to the board to
design database, eliminating the need to allows you to connect it with the rest of
the schematic. This allows logic design
communicate constraints and design data the design and assign constraints to the
and signal integrity design to proceed in
separately. Advanced features include the nest connected to the block.
parallel. The Physical Viewer included with
ability to automatically extract, use, and
Allegro Design Authoring lets you view Multi-Style Design Creation
override constraints from blocks added to
the Allegro PCB Editor. This is beneficial
the design. The Allegro Design Authoring Multi-Style
for viewing ECOs and other documenta-
tion-related issues. Option helps you create design intent for
Constraint Manager presents constraints
complex PCBs faster by letting you use
through several separate worksheets for
Part Development the design style that matches the type
different types of electrical constraints. It
of design. The ability to create different
Allegro Design Authoring solution allows you to capture, manage, and vali-
parts of the same design using differ-
includes Part Developer, which enables date the different rules in a hierarchical
ent paradigms, individually, or as part of
creation and validation of symbols and fashion. Constraint Manager enables you
a team, allows you to capture designs
part data. Part Developer provides a to group all of the high-speed constraints
faster. At the heart of the Multi-Style
powerful mix of functionality that for a collection of signals to form an elec-
Option is a spreadsheet-like interface to
includes the ability to quickly enter and trical constraint set (ECSet). This ECSet is
create design intent. Suitable for large
manipulate data, split pins across multiple then associated with all the nets in the
pin-count devices and backplane designs,
symbols and define visibility for power group. Constraint Manager is integrated
it also allows you to reuse existing sub-
and ground pins. with both Allegro Design Authoring and
sets of the design created in schemat-
the physical design tools, making it easy
AMS Simulation to capture and manage constraints dur-
ics—power supply sections and analog/RF
sections can be reused or integrated easily
Allegro Design Authoring is tightly inte- ing the logical design phase. At any point
in the design.
grated with Allegro AMS Simulator 210 during the design phase, you can launch
for fluid analog simulation. You can con- Constraint Manager to add, view, and The Multi-Style Option also allows mul-
figure schematic symbols to reference manage high-speed constraints in forma- tiple designers to work concurrently on
Spice simulator models and simulate the tion. As the rules are embedded in the a project. The intelligent design differ-
design from within the Allegro Design design, the PCB layout designer can con- ences engine allows teams to simultane-
Authoring environment. You can also centrate on optimizing the physical layout ously compare and reconcile changes
cross-probe between schematic and simu- for size, routability, and manufacturability, when edits are made in logical and physi-
www.cadence.com 3Allegro Design Authoring
cal designs. The Multi-Style Option can neers to specific blocks they are going Additional Utilities
be used throughout the design cycle, to author. It provides a dashboard view
Allegro Design Authoring provides addi-
leveraging existing schematic symbols of the current status of each team mem-
tional tools that shorten the time to
or no schematic symbols at all. The abil- ber’s block. This solution provides much-
author designs:
ity to include schematic blocks and use needed flexibility for large time-critical
schematic libraries protects your cur- projects while accelerating the design • Part Manager tracks part usage to
rent library investment. The Multi-Style creation process. ensure that parts are always in sync
Option also understands extended nets with the design database
SKILL Programming
(Xnets), buses, and differential pairs, and
it provides advanced features for han- • Automatic Table of Contents (TOC)
Engineers can write SKILL programs to
dling terminations, pull-ups, pull-downs, creation and management speeds
customize Allegro Design Authoring and
and decoupling capacitors. It includes an schematic documentation
create custom commands. The custom
online DRC engine, powerful reports, and programs can be used for querying and • Power pin signal assignment automates
schematic generation capabilities that modifying the design data in schematic manual reassignment of power and
make this a complete design solution for sheets. By placing these programs in a ground connectivity commonly needed
PCBs and packages. common area, it’s possible for a team to for large pin-count devices
share the efforts of all team members.
Concurrent Team Design • User-defined mouse strokes allow you
PDF Publishing to execute single or multiple commands
Team design authoring enables mul-
directly from within the canvas without
tiple design engineers to collaborate The Design Publisher Option converts
using the toolbar, menus, or console
asynchro¬nously in the hierarchical devel- Allegro Design Authoring schematics to
opment of a logical design’s definition. content-rich Adobe Portable Document • Function keys streamline design entry
A design can be partitioned into user- Format (PDF) files, creating a secure, tasks by mapping complex or frequently
defined levels of hierarchy and distributed single-file representation of the design. used commands to a single key
to the defined members of the engineer- The PDF files provide navigation through
ing team, provid¬ing them with an iso- the hierarchy as well as access to design
lated “sandbox” for the development and attributes and constraints, making them
verification of their partition(s). ideal for design reviews. Intellectual prop-
erty (IP) is protected through access con-
The Allegro Design Authoring Team
trols that allow you to decide what design
Design Option provides team assignment
data is published for review.
and notification capability to assign engi-
Feature Allegro Design Authoring
Flat, Hierarchical Schematic Creation •
Page Navigation, Management, Hierarchy Viewer •
Variant Editor •
Project Manager •
Cross Referencer •
Archiver •
Design Differences •
Properties Worksheet, Differential Pair Worksheet •
Support for Net Classes •
User Customization •
Part Manager •
Bill-of-Materials Generator •
Physical Design Reuse, Hierarchical Block Reuse •
Import Blocks and Sheets •
Copy Projects or Copy/Paste Within and Between Designs •
Check Plus Rules Checker •
Verilog and VHDL Netlisting •
AMS Integration •
www.cadence.com 4Allegro Design Authoring
Feature Allegro Design Authoring
Build Physical Wizard for Xilinx, Actel, Altera •
Customizable Menus, Custom Commands Using SKILL •
Cross-Probing with PCB Editor •
Electrical Constraints Sets High-Speed Option
Physical, Spacing Constraints High-Speed Option
Same Net Spacing High-Speed Option
High-Speed Model Assignment High-Speed Option
SigXp Topology Editor High-Speed Option
Allegro Viewer Plus High-Speed Option
Component Revision Manager High-Speed Option
Manage Shared Area Team Design Option
Assign, Notify Teams Team Design Option
Dashboard View of Blocks in the Project Team Design Option
Merge / Split Blocks Team Design Option
Locking Team Design Option
Out-of-Date Check Team Design Option
Table / Spreadsheet-Based Design Creation Multi-Style Option
Design Authoring Schematic Block Reuse Multi-Style Option
Import Verilog Netlist from Existing Design Multi-Style Option
Quick Connectivity Creation Functions Multi-Style Option
Import Connectivity using Text Format Multi-Style Option
Online Packaging Multi-Style Option
Associated Components Multi-Style Option
Schematic Generation for Multi-Style Designs Multi-Style Option
Import Verilog Multi-Style Option
Custom Reports Multi-Style Option
TCL Support for Scripting and Extensions Multi-Style Option
Route-Aware Automatic FPGA Pin Assignment FPGA System Planner Option
Automatic Symbol, Schematic Creation for FPGA Sub-System FPGA System Planner Option
Custom-Board ASIC Prototyping with FPGAs FPGA ASIC Prototyping Option
Create and Publish Intelligent PDFs Design Publisher Option
Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
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