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Multiplexers and Signal Switches
Glossary

Application Report

                       Literature Number: SLLA471A
                     MARCH 2020 – REVISED JUNE 2021
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                                                                                                                                  Preface
                                            About This Multiplexers and Signal Switches
                                                                               Glossary

This glossary provides a brief overview and introduction to the terminology, features, and parameters for
multiplexers and signal switches. The entire switches and multiplexers portfolio can be found at www.ti.com/
switches.
For components used to manage power rails, TI offers a power switch and power multiplexer portfolio which can
each be found at www.ti.com/powerswitch.

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www.ti.com                                                                                                                                   Contents

                                                                                                                                   Contents

                                                                Table of Contents

 1. Introduction to Multiplexers and Signal Switches                       2. Operation of Multiplexers and Signal Switches
 •   Signal switch                                                         •   Absolute maximum ratings
 •   Multiplexer (Mux)                                                     •   Recommended operating conditions
 •   Analog switches and multiplexers                                      •   Single power supply
 •   Protocol-specific switches and multiplexers                           •   Dual power supply
 •   Power multiplexer                                                     •   Switch control signal levels (VIH, VIL)
 •   Power switch                                                          •   Rail-to-rail
 •   Precision                                                             •   Input/Output voltage beyond supply
 •   Protection                                                            •   Bidirectional signal path
 •   Low voltage
 •   Mid voltage
 •   Configuration
 •   Channel

 3. Additional Features                                                    4. DC Characteristics
 •   1.8-V control logic                                                   •   On-resistance (RON)
 •   Fail-safe logic                                                       •   On-resistance flatness (RON FLAT)
 •   Injection current control                                             •   OFF leakage current (ID(OFF), IS(OFF))
 •   Integrated pulldown resistor on logic pin                             •   Powered-off I/O pin leakage current (IPOFF)
 •   Latch-up immunity                                                     •   ON leakage current (ID(ON), IS(ON))
 •   Overvoltage protection                                                •   Control input leakage (ISEL or IEN)
 •   Powered-off protection

 5. Dynamic Characteristics                                                6. Timing Characteristics
 •   Off capacitance source and drain (COFF)                               •   Transition time (tTRAN)
 •   On capacitance source and drain (CON)                                 •   Device turn on time from enable pin (tON(EN) and tOFF(EN))
 •   Charge injection (QC)                                                 •   Break-before-make time (tOPEN (BBM))
 •   Off-isolation (OISO)                                                  •   Make-before-break time (tCLOSED (MBB))
 •   Channel-to-channel crosstalk (XTALK)                                  •   Output-to-output skew (tSK)
 •   Bandwidth (BW)                                                        •   Propagation delay through the switch (tpd)

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www.ti.com                                                                                         Introduction to Multiplexers and Signal Switches

                                                                                                                                     Chapter 1
                                      Introduction to Multiplexers and Signal Switches

                                                                                                                 S           D
 Signal switch — An integrated circuit (IC) used for connecting and disconnecting
 an electrical circuit. For more information, see the Switches and muxes: What are
 switches & multiplexers? training video from TI Precision Labs.
                                                                                             Figure 1-1. Ideal 1:1 SPST Switch

                                                                                                                     A0 A1

                                                                                                            S1

                                                                                                            S2
                                                                                                                                 D
 Multiplexer (Mux) — An integrated circuit that connects a selected signal path to a                        S3
 single line.
                                                                                                            S4

                                                                                                     Figure 1-2. Ideal 4:1 Mux

 Analog switches and multiplexers — These devices are used for switching and multiplexing analog and digital signals up to 500 mA in
 applications such as:
 •   Precision data acquisition
 •   GPIO expansion and diagnostics
 •   System communication and bus isolation
 •   System protection and power sequencing
 •   General-purpose signal switching

 Protocol-specific switches and multiplexers — These devices are defined to support specific protocol applications such as USB, HDMI,
 LAN, MIPI, audio, memory and so forth.
 Power multiplexer — These devices are a set of electronic switches used to select and transition between two or more input power paths
 to a single output.
 Power switch — These devices manage power distribution for paths typically greater than 500 mA between a voltage source to a load.
 They can be used to limit inrush current, enable power sequencing, provide protection from overvoltage or overcurrent events, and more.
 Precision — These devices minimize offset error and signal distortion in a high-accuracy measurement system.
 Protection — These devices isolate I/O signal paths and protect the system using powered-off, overvoltage and undershoot protection.
 Low voltage — These devices support I/O signals ≤ ±24 V
 Mid voltage — These devices support I/O signals > ±24 V
 Configuration — Defines the number of signals that can be selected. Table 1-1 shows the typical configurations.
 Channel — Defines the number of configurations (circuits) in a single device. Table 1-1 shows the 1- and 2- channel configurations, but the
 number of channels may exceed 2.

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                                                   Table 1-1. Configurations and Channels
                                                                        1-Channel                                          2-Channel

                                                                                                                            S1     D1
                                                                            S    D
                              1:1                                                                                           S2     D2

                                                                                                                          S1A
                                                                                                                                    D1
                                                                       S1                                                 S1B
                                                                                     D
                              2:1                                      S2                                                 S2A

                                                                                                                                    D2
                                                                                                                          S2B

                                                                                                                          S1A

                                                                                                                          S2B       D1

                                                                       S1
                                                                                                                          S1C
                                                                       S2            D
                              3:1                                                                                         S2A
    Configuration
                                                                       S3
                                                                                                                          S2B       D2

                                                                                                                          S2C

                                                                                                                          S1A

                                                                                                                          S1B
                                                                                                                                    D1
                                                                       S1
                                                                                                                          S1C

                                                                       S2
                                                                                                                          S1D
                                                                                     D
                              4:1                                      S3                                                 S2A

                                                                                                                          S2B
                                                                       S4
                                                                                                                                    D2
                                                                                                                          S2C

                                                                                                                          S2D

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                                 Table 1-1. Configurations and Channels (continued)
                                                              1-Channel                                                2-Channel

                                                                                                                      S1A

                                                                                                                      S1B

                                                                                                                      S1C

                                                                                                                      S1D
                                                                                                                                 D1
                                                              S1                                                      S1E

                                                              S2                                                      S1F

                                                              S3                                                      S1G

                                                              S4                                                      S1H
                                                                         D
   Configuration         8:1                                  S5                                                      S2A

                                                              S6                                                      S2B

                                                              S7                                                      S2C

                                                              S8                                                      S2D
                                                                                                                                 D2
                                                                                                                      S2E

                                                                                                                      S2F

                                                                                                                      S2G

                                                                                                                      S2H

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                                                                                                                                                Chapter 2
                                            Operation of Multiplexers and Signal Switches

 Absolute maximum ratings — These are stress ratings only, which do not imply functional operation of the device at these or any other
 conditions beyond those indicated under the Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for
 extended periods may affect device reliability. Stresses beyond those listed under the Absolute Maximum Rating may cause permanent
 damage to the device.
 Recommended operating conditions — The operating conditions for which the device has been characterized.
                                                                                                                     Single            Dual
                                                                                                                     Supply:          Supply:
                                                                                                      VDD (+V)

 Single power supply — Device with only positive power supply pins with
 reference to ground. The voltage applied is labeled as VDD, VCC, V+ and so
 forth.                                                                                                    GND
 Dual power supply — Device with positive and negative supply pins with
 reference to ground. Voltage applied at the positive pin is labeled as VDD, VCC,
 V+, and so forth, and at the negative pin is labeled as VSS, VEE, V-, and so
 forth.
                                                                                                      VSS (-V)

                                                                                           Figure 2-1. Single and Dual Supply

                                                                                                                     V DD

                                                                                                                             Log ic
 Switch control signal levels (VIH, VIL) — Voltage levels required on the                                                   ³HIG H´
 control pins (EN, SEL, IN, and so forth) required for the switch to change the
 internal signal path.                                                                                               VIH

 •   VIH – The minimum voltage for the input control signal to achieve a logic
     "1"high value                                                                                                   VIL
                                                                                                                             Log ic
 •   VIL – The maximum voltage for the input control signal to remain a logic
                                                                                                                            ³LOW´
     "0"low value                                                                                                    GND

                                                                                       Figure 2-2. Switch Control Signal Levels

                                                                                                    VDD
                                                                                                              VI/O

 Rail-to-rail — A common term meaning that a device will support VI/O voltage
 range between the most positive and most negative power supply rails.
                                                                                                0V
                                                                                              (GND)
                                                                                                                                                 t

                                                                                                      Figure 2-3. Rail-to-Rail

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                                                                                             VI/O(MAX)

                                                                                                    VDD

 Input/Output voltage beyond supply – The switch can support voltage range
 beyond the supply rail to VI/O(MAX)as indicated by the recommended operating
 conditions.
                                                                                                 0V
                                                                                               (GND)
                                                                                                                                       t

                                                                                         Figure 2-4. I/O Voltage Beyond Supply

                                                                                                                  A0   A1

                                                                                                          S1

                                                                                                          S2
 Bidirectional signal path – The switch conducts equally well from source
 (S) to drain (D) or from drain (D) to source (S). Each channel has very                                                         D
 similar characteristics in both directions and supports both analog and digital                          S3
 signals. TI analog switches and multiplexers are typically bidirectional. See the
 Switches and muxes: Are switches & multiplexers bidirectional? training video                            S4
 from TI Precision Labs.

                                                                                          Figure 2-5. Bidirectional Signal Path

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                                                                                                                                                   Chapter 3
                                                                                                                  Additional Features

 1.8-V control logic – Switches with this feature have a built-in voltage translator to prevent voltage mismatch between the supply rail and
 the control logic. VIH and VIL levels are compatible with the 1.8-V logic levels at any voltage supply. See the Simplifying Design With 1.8 V
 logic MUXes and Switches Tech Note for more information.

                                                                                                                                       VDD = 0 V

                                                                        VCC = 5 V                                    VDD
                                                                                                Protection
                                                                                        VSEL

 Fail-safe logic – Ensures the switch stays off and                           0V
 the voltage on the logic pin (VSEL) does not back-
                                                                  Subsystem                    SEL
 power VDD when VSEL is greater than VDD. See the                     A
 Switches and muxes: What is fail-safe logic? training
                                                                                                                                            Subsystem
 video from TI Precision Labs.                                                                                                                  B
                                                                                               S                      High-Z       D

                                                                                    Figure 3-1. Fail-Safe Logic

 Injection current control — Allows signals on                                            S1                                   D
 disabled (high-Z) signal paths to exceed the supply
 voltage without affecting the signal of the enabled                                               Control
 signal path. For example, if current is injected into                                             Circuitry
 a disabled signal path, raising the voltage at the
                                                                                          S2
 pin above the supply, the signal on the enabled
 signal path will not be affected. See the Switches
                                                                                                   Control
 and muxes: Prevent crosstalk with injection current                                +              Circuitry
 control training video from TI Precision Labs.
                                                                                    ±

                                                                            Figure 3-2. Injection Current Control

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                                                                                                           VDD

                                                                                                  S                                  D

                                                                                                 EN
 Integrated pulldown resistor on logic pin –
 Internal weak pulldown resistors to GND to ensure
 the logic pins are not floating.
                                                                                                                  GND

                                                                        Figure 3-3. Integrated Pulldown Resistor on Logic Pin

                                                                                     NMOS                                                PMOS        VDD

                                                                                           Gate                                      Gate

                                                                            GND

 Latch-up immunity – Devices that are latch-up

                                                                                                             Trench Oxide

                                                                                                                                                             Trench Oxide
                                                             Trench Oxide

 immune are built in a Silicon On Insulator (SOI)                              p+    n+               n+                        p+              p+   n+
 process and will not latch-up when exposed to
 current injection or overvoltage events. See the                           p-epi                                           n-well
 Switches and muxes: What is latch-up immunity?
 training video from TI Precision Labs.
                                                            Buried Oxide Layer (Insulator)

                                                            Substrate (p) / Handle

                                                                             Figure 3-4. Latch-Up Immunity With SOI Process

                                                                                          VI/O(MAX)

                                                                                                                   Switch
                                                                                                                   ³2))´

 Overvoltage protection – When the input voltage                                                VTH                                      VI/O
 VI/O exceeds the defined threshold voltage, VTH,
 the switch enters the high impedance state, isolates
 signal path, and protects downstream components.                                                           6ZLWFK ³21´

                                                                                          VI/O(MIN)

                                                                                    Figure 3-5. Overvoltage Protection

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                                                                                                                        VDD = 0 V

                                                                                                     VDD

 Powered-off protection – Protects switch and                              VCC = 5 V
 isolates signal path when signals are present at the                                       Pro tection
 I/O pins and VDD = 0 V. See the Switches and                                                                     SEL
 muxes: Simplify power sequencing with powered-off                                     VS
 protection training video from TI Precision Labsand               Sub system 0 V               IS                             Sub system
 the Eliminate Power Sequencing With Powered-off                        A                   S         High-Z        D               B
 Protection Signal Switches Tech Note for more
 information.

                                                                            Figure 3-6. Powered-Off Protection

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www.ti.com                                                                                                                                          DC Characteristics

                                                                                                                                                         Chapter 4
                                                                                                                            DC Characteristics

For more parameter information, see the device data sheet.
                                                                                                                                   VDD

                                                                                                                                   RON
                                                                                                                  S1                                D1

 On-resistance (RON) — The resistance inserted into the signal path as a
 result of the switch path being turned on.                                                        +
                                                                                         VS                                                                   RL
                                                                                                   ±                            Switch ON

                                                                                               Figure 4-1. On-Resistance

                                                                                                   RON FLAT ( )
                                                                                                                                    Flatness

 On-resistance flatness (RON FLAT) — Difference between the maximum and
 minimum value of Ron in a channel over the VD or VS voltage range.

                                                                                                                                VD or VS (V)

                                                                                       Figure 4-2. On-Resistance Flatness

                                                                                                                                    VDD

                                                                                                                       S1   S           D      D1
                                                                                                                                 Hi-Z
 OFF leakage current (ID(OFF), IS(OFF)) — Leakage current measured at the                                     +                     ID(OFF)
 input port, with the corresponding channel output in the OFF state under                     VS                                                         RL
                                                                                                              ±
 worst-case input and output conditions.

                                                                                                                                Switch OFF

                                                                                         Figure 4-3. OFF Leakage Current

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                                                                                                                               0V

                                                                                                                   Protection

                                                                                                                  IPOFF
                                                                                                            S1                S Hi-Z D     D1

 Powered-off I/O pin leakage current (IPOFF) — The leakage current flowing                            +
 into or out of the source pin when the device is powered off (VDD = 0V).                     VS                                                     RL
                                                                                                      ±
                                                                                                                        Switch OFF

                                                                                      Figure 4-4. Powered-Off I/O Pin Leakage
                                                                                                      Current

                                                                                                                               VDD

                                                                                                      IS                                        ID
                                                                                                             S1        S                   D1
                                                                                                                              ON D

                                                                                                      +                        ID(ON)
 ON leakage current (ID(ON), IS(ON)) — Leakage current measured at the input                  VS                                                     RL
                                                                                                                                 or
 port in the ON state, with the corresponding output port in the ON state and                         ±
                                                                                                                               IS(ON)
 the output being open.
                                                                                                                           Switch ON
                                                                                                                              IS • ,D

                                                                                            Figure 4-5. ON Leakage Current

                                                                                                                                    VDD

                                                                                                                  S1           S Hi-Z D         D1

 Control input leakage (ISEL or IEN) — Leakage measured at the switch                                            EN
 control pins.                                                                                      VSEL               ISEL
                                                                                                     or                  or
                                                                                                                        IEN
                                                                                                    VEN
                                                                                                                              Switch OFF

                                                                                           Figure 4-6. Control Input Leakage

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www.ti.com                                                                                                                 Dynamic Characteristics

                                                                                                                                     Chapter 5
                                                                                         Dynamic Characteristics

For detailed information of dynamic characteristics, see the Multiplexers: Bandwidth, Channel-to-Channel
Crosstalk, Off-Isolation and THD+Noise training video from TI Precision Labs.
For more parameter information, see the device data sheet.
                                                                                                                 VDD

                                                                                                S1            S Hi-Z D         D1

                                                                                                     COFF
 Off capacitance source and drain (COFF) — The capacitive loading when a
 switch path is in the high-impedance state.                                            VS                                           RL
                                                                                                             Switch OFF

                                                                             Figure 5-1. Source and Drain Off Capacitance

                                                                                                                 VDD

                                                                                               S1            S   ON D           D1
                                                                                                    CS(ON)        CD(ON)
 On capacitance source and drain (CON) — The capacitive loading when a
                                                                                       VS                                             RL
 switch path is in the low-impedance state.
                                                                                                             Switch ON

                                                                                                       CON = CS(ON) + CD(ON)

                                                                             Figure 5-2. Source and Drain On Capacitance

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                                                                                                                               VDD

                                                                                                                S1         S           D    D1

                                                                                                +
                                                                                         VS                 EN                                      CL        RL
                                                                                                ±

                                                                                                    VE
                                                                                                    N

 Charge injection (QC) — Charge injection is a measurement of unwanted
                                                                                                    VDD
 signal coupling from the control (EN) input to the analog output. This is                 VEN
 measured in coulomb (C) and measured by the total charge induced due to
 switching of the control input.                                                                    0V

                                                                                                    VDD
                                                                                                                                             ¨9D1
                                                                                           VD1
                                                                                                                          ¨9D1

                                                                                                    0V

                                                                                                                          QC = CL * ¨9D

                                                                                                    Figure 5-3. Charge Injection

                                                                                                                                VDD

                                                                                                          VS1
                                                                                                                                                  VD1

                                                                                                                S1        S           D      D1
                                                                                                                               Hi-Z
 Off-isolation (OISO) — A measurement OFF-state switch impedance. This
 is the ratio of VD1 to VS1 measured in dB at a specific frequency, with the                  VS                                                         RL
 corresponding channel in the OFF state.                                                                                  Switch OFF

                                                                                                         Figure 5-4. Off-Isolation

                                                                                                                                      VDD

                                                                                                          VS1

                                                                                                                     S1          S    ON D        D1

                                                                                                     +
                                                                                          VS1                                                            RL
                                                                                                     ±

 Channel-to-channel crosstalk (XTALK) — A measurement of unwanted
 signal coupling from an ON channel to an OFF channel. This is the ratio                                  VS2
                                                                                                                     S2          S Hi-Z D         D2
 of VS2 to VS1 measured in dB at a specific frequency.
                                                                                                     +
                                                                                          VS2                                                            RL
                                                                                                     ±

                                                                                                                      XTALK =

                                                                                     Figure 5-5. Channel-to-Channel Crosstalk

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                                                                                          Magnitude (dB)
                                                                                                                   í3 dB

                                                                                                               Ban dwidth
 Bandwidth (BW) — The frequency range of signals that can pass through
 the switch with no more than 3 dB of attenuation.
                                                                                                                  Freque ncy (Hz)

                                                                                                           Figure 5-6. Bandwidth

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www.ti.com                                                                                                                            Timing Characteristics

                                                                                                                                             Chapter 6
                                                                                                     Timing Characteristics

For detailed information, see the Switches and muxes: What are timing characteristics? training video from TI
Precision Labs.
For more parameter information, see the device data sheet.
                                                                                                                            VDD

                                                                                                                S1     S          D     D1
                                                                                                                            ON

                                                                                                    +
                                                                                             VS                                                 RL
                                                                                                    ±
                                                                                                           SEL

                                                                                                  VSEL                Switch ON

 Transition time (tTRAN) — The time taken by the switch output to rise or fall
 within a given percentage of the final value after the address signal has risen
 or fallen past the logic threshold.                                                                      VDD
                                                                                                                        VIH
                                                                                                  VSEL
                                                                                                                                  VIL
                                                                                                          0V
                                                                                                                       tTRAN
                                                                                                          VS
                                                                                                                           90%
                                                                                                    VD1

                                                                                                                                          10%
                                                                                                          0V

                                                                                                  Figure 6-1. Transition Time

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                                                                                                                                VDD

                                                                                                                  S1        S      ON      D         D1

                                                                                                 +               EN
                                                                                           VS                                                                 RL
                                                                                                 ±

                                                                                                                            Switch ON
                                                                                                     VEN

 Device turn on time from enable pin
 (t ON(EN) and t OFF(EN) ) — The time taken by the switch output to rise or fall                           VDD
                                                                                                                                               VIH
 within a given percentage of the final value after the enable has risen or fallen                   VEN
 past the logic threshold.                                                                                                   VIL
                                                                                                           0V
                                                                                                                            tON (EN)                      tOFF (EN)
                                                                                                           VS
                                                                                                                                   90%                    90%
                                                                                                     VD1

                                                                                                           0V

                                                                                     Figure 6-2. Device Turn on Time From Enable
                                                                                                          Pin

                                                                                                                             VDD

                                                                                                            S1A         S           D            D1

                                                                                                 +                                                    RL           CL
                                                                                           VS
                                                                                                 ±
                                                                                                            S1B         S           D

                                                                                                           SEL

                                                                                                VSEL
 Break-before-make time (tOPEN (BBM)) — Ensures that in a multiplexer, two
 multiplexer paths are never electrically connected when the signal path is
 changed by the select input.
                                                                                                     VDD
                                                                                                 VSEL
                                                                                                      0V

                                                                                                       VS
                                                                                                                  90%
                                                                                                 VD1
                                                                                                                                   tBBM1                     tBBM2
                                                                                                       0V

                                                                                                                   tOPEN (BBM) = min ( tBBM1, tBBM2)

                                                                                          Figure 6-3. Break-Before-Make Time

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                                                                                                                              VDD

                                                                                                            S1          S            D          D1A

                                                                                            +                                                          RL        CL
                                                                                       VS
                                                                                            ±

                                                                                                                        S            D          D 1B
                                                                                                          SEL
                                                                                                                                                       RL        CL
                                                                                            VSEL

 Make-before-break time (tCLOSED (MBB)) — Ensures that in a multiplexer, two
 multiplexer paths are never electrically disconnected when the signal path is
 changed by the select input.                                                                             VDD
                                                                                                VSEL                         VIH
                                                                                                          0V
                                                                                                          VS
                                                                                                                                         90%
                                                                                                VD1A
                                                                                                          0V
                                                                                                          VS
                                                                                                                            90%
                                                                                             VD1B

                                                                                                          0V
                                                                                                                tCL OS ED (MBB)

                                                                                        Figure 6-4. Make-Before-Break Time

                                                                                                                                   VDD

                                                                                                                 S1           S     ON D          D1

                                                                                                      +
                                                                                            VS                                                              RL
                                                                                                      ±

                                                                                                                 S2           S     ON D          D2

                                                                                                      +
                                                                                            VS                                                              RL
                                                                                                      ±
 Output-to-output skew (tSK) — The maximum difference between the                                                           Switches ON
 propagation delays of different outputs due to different internal paths.
                                                                                                       VS
                                                                                                VD1                         50%           50%
                                                                                                      0V

                                                                                                                              tSK1       tSK2
                                                                                                       VS
                                                                                                VD2                         50%            50%
                                                                                                      0V
                                                                                                                        tSK = max ( tSK1, tSK2)

                                                                                         Figure 6-5. Output-to-Output Skew

SLLA471A – MARCH 2020 – REVISED JUNE 2021                                                                   Multiplexers and Signal Switches Glossary                 25
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                                                                                                                              VDD

                                                                                                              S1          S    ON D            D1

                                                                                                       +
                                                                                               VS                                                   RL
                                                                                                       ±                Switch ON

                                                                                                  VS
 Propagation delay through the switch (tpd) — The time required for a                       VS1                      50%            50%
 signal to pass from the input signal pin to the respective output signal pin.                    0V

                                                                                                                      tPD 1         tPD 2
                                                                                                  VS
                                                                                            VD1                                        50
                                                                                                                      50%
                                                                                                                                       %
                                                                                                  0V
                                                                                                                   tpd = max ( tPD 1, tPD 2)

                                                                                     Figure 6-6. Propagation Delay Through the
                                                                                                       Switch

26     Multiplexers and Signal Switches Glossary                                                           SLLA471A – MARCH 2020 – REVISED JUNE 2021
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