Alveo Card Management Solution Subsystem v4.0
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Alveo Card Management Solution Subsystem v4.0 Product Guide PG348 (v4.0) April 29, 2022 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve launched an internal initiative to remove language that could exclude people or reinforce historical biases, including terms embedded in our software and IPs. You may still find examples of non-inclusive language in our older products as we work to make these changes and align with evolving industry standards. Follow this link for more information.
Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Features........................................................................................................................................ 4
IP Facts..........................................................................................................................................5
Navigating Content by Design Process.................................................................................... 6
Applications..................................................................................................................................6
Licensing and Ordering.............................................................................................................. 7
Chapter 2: Overview......................................................................................................8
Sensor Monitoring...................................................................................................................... 8
Mailbox Interface...................................................................................................................... 12
Satellite Controller Firmware Update..................................................................................... 13
Card Information Reporting.................................................................................................... 19
Network Plug-in Module Management.................................................................................. 25
SN1000 SoC Management........................................................................................................34
Chapter 3: Product Specification......................................................................... 40
Performance.............................................................................................................................. 40
Resource Utilization.................................................................................................................. 40
Port Descriptions.......................................................................................................................41
Register Space........................................................................................................................... 42
Chapter 4: Designing with the Subsystem..................................................... 54
Clocking...................................................................................................................................... 54
Resets..........................................................................................................................................54
Addressing................................................................................................................................. 54
Interrupts................................................................................................................................... 55
Chapter 5: Design Flow Steps.................................................................................56
Customizing and Generating the Subsystem........................................................................ 56
Constraining the Subsystem....................................................................................................57
Simulation.................................................................................................................................. 59
Synthesis and Implementation................................................................................................59
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CMS Subsystem Product Guide 2Chapter 6: Example Design..................................................................................... 60
Overview.....................................................................................................................................60
Implementing the Example Design........................................................................................ 61
Example Design Files................................................................................................................ 62
Appendix A: Upgrading............................................................................................. 63
Changes from v3.0 to v4.0........................................................................................................63
Changes from v2.0 to v3.0........................................................................................................63
Changes from v1.0 to v2.0........................................................................................................64
Appendix B: Debugging.............................................................................................65
Finding Help on Xilinx.com...................................................................................................... 65
Debug Tools............................................................................................................................... 66
Hardware Debug....................................................................................................................... 67
Appendix C: Additional Resources and Legal Notices............................. 68
Xilinx Resources.........................................................................................................................68
Documentation Navigator and Design Hubs.........................................................................68
References..................................................................................................................................68
Revision History......................................................................................................................... 69
Please Read: Important Legal Notices................................................................................... 71
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CMS Subsystem Product Guide 3Chapter 1: Introduction
Chapter 1
Introduction
The Alveo™ Card Management Solution Subsystem (CMS Subsystem) is a MicroBlaze™-based
design compatible with U200, U250, U280, U50, U55, SN1000, X3522, and next-generation
Alveo acceleration cards.
CMS firmware autonomously reads sensor information from the satellite controller device over
UART and writes instantaneous, maximum, and average values to a shared memory for collection
by the host software. Sensor information is monitored and gathered for:
• Voltages
• Currents
• Temperatures
• Fan speed
• Power
The CMS solution also provides a message based mailbox interface to enable other card
management functions including:
• Satellite controller firmware updates
• Card information reporting
• Network plug-in module management
• SN1000 SoC management
Features
Table 1: Features
Feature Description
Sensor Monitoring Reports key voltage rails, current values, temperatures, power values, and fan
speed from the satellite controller.
Card Information Reports card information from the satellite controller, including MAC
addresses.
Satellite Controller Firmware Update Provides satellite controller firmware update interface.
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CMS Subsystem Product Guide 4Chapter 1: Introduction
Table 1: Features (cont'd)
Feature Description
Network Plug-in Module Management Provides read/write access to network plug-in module I2C interface.
Provides status and control of network plug-in module low speed I/O.
IP Facts
LogiCORE™ IP Facts Table
Subsystem Specifics
Supported Device Family1 UltraScale+™
Note: This solution is targeted to U200, U250, U280, U50, U55, SN1000, X3522, and
next-generation Alveo cards.
Supported User Interfaces AXI4-Lite
Resources Performance and Resource Use web page
Provided with Subsystem
Design Files IP integrator HIP Subsystem
Example Design VHDL/Verilog
Test Bench N/A
Constraints File Xilinx Design Constraints (XDC)
Simulation Model N/A
Supported S/W Driver N/A
Tested Design Flows2
Design Entry Vivado® Design Suite
Simulation N/A.
Synthesis N/A
Support
All Vivado IP Change Logs Master Vivado IP Change Logs: Xilinx Answer Record 72775
Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP catalog.
2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
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CMS Subsystem Product Guide 5Chapter 1: Introduction
Navigating Content by Design Process
Xilinx® documentation is organized around a set of standard design processes to help you find
relevant content for your current development task. All Versal® ACAP design process Design
Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This
document covers the following design processes:
• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware
platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing,
resource use, and power closure. Also involves developing the hardware platform for system
integration. Topics in this document that apply to this design process include:
• Port Descriptions
• Register Space
• Clocking
• Resets
• Chapter 6: Example Design
Applications
The CMS Subsystem is designed for in-band card management systems for plug-in PCIe® cards
for servers typically deployed in data centers.
A typical configuration deployment configuration is shown in Figure 1.
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CMS Subsystem Product Guide 6Chapter 1: Introduction
Figure 1: CMS Subsystem Typical Configuration
Shell
Host MicroBlaze Communication
Register
PCIe PCIe Sensors
CPU Subsystem Map
AXI BRAM MicroBlaze Satellite Controller
(REG_MAP) Communication
AXI UART
UART ...
Satellite
GPIO Controller
SM LMB
Bus MicroBlaze
BMC
LMB Memory
Management AXI
RESET MicroBlaze LITE Network
*HBM Temp1, Plug-in
MicroBlaze HBM Temp2 Modules
Reset AXI INT
GPIO AXI *HBM
GPIO IP ...
(MB_RESETN
_REG)
WatchDog
Timer
Host
Interrupt
Controller
Host (HOST_INTC) Interrupt
Interrupt *HBM CATTRIP
Controller
Interrupt
Server Alveo
Card Management Solution (CMS) Subsystem
*U50/U280/U55 and next-generation Alveo cards only
X22660-120921
Licensing and Ordering
This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®
Design Suite under the terms of the Xilinx End User License.
Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx Intellectual
Property page. For information about pricing and availability of other Xilinx LogiCORE IP modules
and tools, contact your local Xilinx sales representative.
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CMS Subsystem Product Guide 7Chapter 2: Overview
Chapter 2
Overview
The CMS solution is the MicroBlaze™ microprocessor and firmware solution. Software
configuration of the CMS subsystem is not required (the CMS is fixed function).
The recommended satellite controller firmware versions compatible with the latest CMS
firmware are listed in Table 2.
Table 2: CMS and Satellite Controller Firmware Compatibility
CMS Firmware Version Alveo Card Satellite Controller Firmware Version
1.2.23 (0x0C010217) U200/U250 4.6.20
1.3.3 (0x0C010303) U280 4.3.22
1.0.40 (0x0C010028) U50 5.2.18
1.5.25 (0x0C010519) U55 7.1.17
1.9.12 (0x0C01090C) SN1000 3.0.18
1.10.17 (0x0C010A11) X3522 3.0.18
1.5.25 (0x0C010519) Next-generation 7.1.17
Notes:
1. In the 2022.1 release the SC FW has been updated for the U50/U200/U250/U280 cards to use the legacy MAC
addressing scheme. For more information, see Alveo - Custom Flow - CMS IP - 2022.1 MAC Addressing.
RECOMMENDED: The CMS IP is also backward compatible with the default satellite controller firmware
shipped with Alveo cards, but may not support the latest functions and capabilities. Upgrade the Alveo
card satellite controller firmware to the version listed in Table 2. For more information on upgrading to the
latest firmware refer to Getting Started with Alveo Data Center Accelerator Cards (UG1301).
Sensor Monitoring
CMS firmware polls for sensor information from the satellite controller approximately every 120
ms, communicating via a UART interface and GPIO handshake lines. CMS firmware then
processes sensor information and writes instantaneous, maximum, and average values to a
shared memory (memory mapped) for collection by the host software. The host software must
poll the shared memory (REG_MAP) for updated sensor information.
Sensor information is gathered and monitored for:
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CMS Subsystem Product Guide 8Chapter 2: Overview
• Voltage
• Current
• Temperature
• Power
• Fan Speed
Note: Fan speed is reported only for active cards with local fans. Passive cards do not contain fans.
Note: HBM Temperature reporting must be enabled on compatible Alveo cards via the REG_MAP control
register (CONTROL_REG).
Figure 2: Card Management Solution Subsystem Block Diagram
Host MicroBlaze Communication
Host AXI LITE Register Map
Interface AXI BRAM
(REG_MAP)
UART
AXI UART Satellite
Controller
LMB GPIO Interface
MicroBlaze X2/4
LMB Memory AXI
RESET LITE
Management
MicroBlaze
INT
*HBM
MicroBlaze AXI GPIO Temp
Reset AXI GPIO x2
(MB_RESETN_REG)
WatchDog
Timer
Host Interrupt
Host Interrupt Controller
(HOST_INTC)
HBM*
CATTRIP
Interrupt
Interrupt
Controller
Card Management Solution (CMS) Subsystem
*U50/U280/U55 and next-generation Alveo cards only
X23179-120921
Table 3: Supported Sensors per Alveo Card
Sensor Name U200/U250 U280 U50 U55 SN1000 X3522
1V2_VCCIO
2V5_VPP23
3V3_AUX ✓ ✓ ✓
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CMS Subsystem Product Guide 9Chapter 2: Overview
Table 3: Supported Sensors per Alveo Card (cont'd)
Sensor Name U200/U250 U280 U50 U55 SN1000 X3522
3V3_PEX ✓ ✓ ✓ ✓ ✓ ✓
3V3PEX_I_IN ✓ ✓ ✓ ✓
12V_AUX ✓ ✓ ✓ ✓
12V_AUX1
12V_AUX_I_IN ✓ ✓ ✓ ✓
12V_PEX ✓ ✓ ✓ ✓ ✓ ✓
12V_SW ✓ ✓
12VPEX_I_IN ✓ ✓ ✓ ✓ ✓ ✓
AUX_3V3_I ✓
CAGE_TEMP0 ✓ ✓ ✓ ✓ ✓ ✓
CAGE_TEMP1 ✓ ✓ ✓ ✓ ✓
CAGE_TEMP2
CAGE_TEMP3
DDR4_VPP_BTM ✓ ✓
DDR4_VPP_TOP ✓ ✓
DIMM_TEMP0 ✓ ✓
DIMM_TEMP1 ✓ ✓
DIMM_TEMP2 ✓
DIMM_TEMP3 ✓
FAN_SPEED ✓ ✓
FAN_TEMP ✓ ✓
FPGA_TEMP ✓ ✓ ✓ ✓ ✓ ✓
GTAVCC
GTVCC_AUX
HBM_1V2 ✓ ✓
HBM_1V2_I ✓
HBM_TEMP1 ✓ ✓ ✓
HBM_TEMP2 ✓ ✓ ✓
MGT0V9AVCC ✓ ✓ ✓ ✓
MGTAVTT ✓ ✓ ✓ ✓
PEX_3V3_POWER ✓
PEX_12V_POWER ✓
POWER_GOOD ✓ ✓ ✓ ✓ ✓ ✓
SE98_TEMP0 ✓ ✓ ✓ ✓ ✓ ✓
SE98_TEMP1 ✓ ✓ ✓ ✓ ✓ ✓
SE98_TEMP2 ✓
SYS_5V5 ✓ ✓ ✓ ✓
V12_IN_AUX0_I
V12_IN_AUX1_I
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CMS Subsystem Product Guide 10Chapter 2: Overview
Table 3: Supported Sensors per Alveo Card (cont'd)
Sensor Name U200/U250 U280 U50 U55 SN1000 X3522
V12_IN_I
VCC0V85 ✓ ✓
VCC1V2_BTM ✓ ✓
VCC1V2_I
VCC1V2_TOP ✓ ✓
VCC1V8 ✓ ✓ ✓ ✓ ✓ ✓
VCC3V3 ✓ ✓ ✓ ✓
VCC_5V0
VCCAUX
VCCAUX_PMC
VCCINT ✓ ✓ ✓ ✓ ✓ ✓
VCCINT_I ✓ ✓ ✓ ✓ ✓ ✓
VCCINT_IO ✓ ✓
VCCINT_IO_I ✓ ✓
VCCINT_POWER
VCCINT_TEMP ✓ ✓ ✓ ✓ ✓
VCCINT_VCU_0V9
VCCRAM
VCCSOC
VPP2V5 ✓ ✓
Notes:
1. ✓ indicates the sensor is supported and no entry indicates the sensor is not supported.
Card Power Calculations
Power figures can be calculated by combining voltage and current sensor values for each power
domain, as described in Table 4.
The total card power is calculated by combining the power figures for each domain:
Total Power = 12V_AUX Power + 12V_PEX Power + 3V3_PEX Power + 3V3_AUX Power
The following table defines the active power domains on each Alveo card.
Table 4: Alveo Card Power Calculations
Power Domain U200/U250 U280 U50 U55 SN1000 X3522
12V_AUX Power = ✓ ✓ ✓ ✓
12V_AUX x 12V_AUX_I_IN
12V_PEX Power = ✓ ✓ ✓ ✓ ✓ ✓
12V_PEX x 12V_PEX_I_IN
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CMS Subsystem Product Guide 11Chapter 2: Overview
Table 4: Alveo Card Power Calculations (cont'd)
Power Domain U200/U250 U280 U50 U55 SN1000 X3522
3V3_PEX Power = ✓ ✓ ✓ ✓
3V3_PEX x 3V3_PEX_I_IN
3V3_AUX Power = ✓
3V3_AUX x AUX_3V3_I
Mailbox Interface
A section of the register map is reserved for a dedicated host to the CMS mailbox interface. The
mailbox may be used to request the satellite controller firmware update, card information
reporting, and network plug-in module management functions.
Details of the messages used for each function are defined in the relevant subsections within this
document.
Message Format
Each request message written to the mailbox contains a 32-bit header. Request messages may
also contain payload information depending on the function requested. Mailbox response
payload is written to remaining words of the mailbox buffer. The format of the Header is defined
in the following table.
Table 5: Message Header Format
Message Header [31:24] Message Header [23:12] Message Header [11:0]
Opcode Reserved Message Length (bytes)1
Notes:
1. This field is only used for certain messages and may be populated as part of the Host Request Message or CMS
Response Message. Further details can be found in the mailbox feature subsections.
Using the Mailbox
The mailbox start location within the register map (REG_MAP) is defined by register
HOST_MSG_OFFSET_REG.
The following details the mailbox operation.
1. The host checks the availability of the mailbox by confirming CONTROL_REG[5] is 0.
2. The host writes a request message to the mailbox.
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CMS Subsystem Product Guide 12Chapter 2: Overview
3. The host sets CONTROL_REG[5] to 1 to indicate a new request message is available to CMS
firmware.
4. The host polls CONTROL_REG[5] until CMS firmware sets to 0, indicating the CMS response
message is in the mailbox.
5. The host reads HOST_MSG_ERROR_REG to confirm no message errors are present.
6. If no errors are reported, the host reads the response message from the mailbox.
Note: The format of request and response messages for each mailbox feature is defined in the relevant
subsections within this document.
Figure 3: Mailbox Layout
0x18 CONTROL_REG
0x300 HOST_MSG_OFFSET_REG
0x304 HOST_MSG_ERROR_REG
MAILBOX OFFSET
REG_MAP Offset
0x28000-029FFF
MAILBOX
X25352-061021
Satellite Controller Firmware Update
Satellite controller firmware can be updated using the mailbox interface.
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CMS Subsystem Product Guide 13Chapter 2: Overview
Note: A tool has been provided to perform the satellite controller firmware upgrade. Refer to Xilinx Answer
Record 73654 for more information.
Satellite controller firmware images are formatted text files. The firmware image is split into
sections, as shown in Figure 4. The sections are transferred in chunks if they are too big to
transfer in a single mailbox message.
Figure 4: Satellite Firmware Message
Start Address @0200
0C 48 08 B5 80 F3 08 88 09 49 08 68 40 F4 70 00
08 60 00 BF 00 BF 17 F0 B2 FF 08 B1 16 F0 1A FC
00 20 0D F0 B1 FA 01 20 17 F0 AB FF 08 BD C0 46
88 ED 00 E0 00 00 01 20 1C B5 8D F8 04 00 00 20
8D F8 05 00 C1 48 9D F8 04 10 00 EB 01 10 00 90
Firmware Data ... Section 1
00 6C FF F7 5D BC 40 8B 00 F0 08 00 70 47 40 68
80 6D FF F7 55 BC 08 B5 FC F7 C8 FB 08 BD 6F F0
01 00 70 47 6F F0 01 00 70 47 6F F0 01 00 70 47
6F F0 02 00 70 47 30 BF 70 47 00 20 70 47 01 20
70 47 00 BF FE E7
Start Address @18188
00 00 00 00 96 30 07 77 2C 61 0E EE BA 51 09 99
19 C4 6D 07 8F F4 6A 70 35 A5 63 E9 A3 95 64 9E
32 88 DB 0E A4 B8 DC 79 1E E9 D5 E0 88 D9 D2 97
2B 4C B6 09 BD 7C B1 7E 07 2D B8 E7 91 1D BF 90
64 10 B7 1D F2 20 B0 6A 48 71 B9 F3 DE 41 BE 84
Firmware Data ... Section 2
29 58 01 00 35 80 01 00 81 80 01 00 00 00 00 00
02 00 00 00 00 A1 00 00 02 00 00 00 E8 00 00 00
F8 94 01 00 00 A1 00 20 78 98 01 00 00 00 00 20
80 98 01 00 00 B8 00 20
Start Address @0000
00 00 01 20 B9 7E 01 00 FF 12 01 00 F5 7F 01 00
E5 7F 01 00 E5 7F 01 00 E5 7F 01 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 CD 2E 01 00
E5 7F 01 00 00 00 00 00 6D 2E 01 00 E9 76 01 00
E5 7F 01 00 E5 7F 01 00 E5 7F 01 00 E5 7F 01 00
Firmware Data ... Section 3
E5 7F 01 00 E5 7F 01 00 E5 7F 01 00 E5 7F 01 00
E5 7F 01 00 E5 7F 01 00 E5 7F 01 00 E5 7F 01 00
E5 7F 01 00 E5 7F 01 00 E5 7F 01 00 E5 7F 01 00
E5 7F 01 00 E5 7F 01 00 E5 7F 01 00 E5 7F 01 00
E5 7F 01 00
q
X25353-061421
The messages required to perform this function are defined in the following table.
Table 6: Message Header Opcodes
Opcode Name Description
0x5 CMS_OP_SC_FW_ERASE Performs mass erase on the satellite controller flash to
remove old firmware image.
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CMS Subsystem Product Guide 14Chapter 2: Overview
Table 6: Message Header Opcodes (cont'd)
Opcode Name Description
0x1 CMS_OP_SC_FW_SEC Starts the update of a firmware section in the Satellite
Controller flash. This message will provide the start location
and the total length of the section to be transferred. The
message also contains payload data for the firmware section.
If the section is too big for a single message additional chunks
are sent using CMS_OP_SC_FW_DATA messages.
0x2 CMS_OP_SC_FW_DATA Continues update of a firmware section in the satellite
controller flash. This message will send additional chunks of
the firmware section being updated.
0x3 CMS_OP_SC_FW_REBOOT Forces the satellite controller to reboot with new firmware
image.
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CMS Subsystem Product Guide 15Chapter 2: Overview
Figure 5: Satellite Controller Firmware Update Flow Chart
Start Firmware Update
CMS_OP_SC_FW_ERASE
Firmware section
Mailbox buffer size Mailbox buffer size
AND Repeat until entire
Another section needs section is written
update
CMS_OP_SC_FW_SEC CMS_OP_SC_FW_DATA
Current section complete
Firmware sectionChapter 2: Overview
CMS_OP_SC_FW_ERASE (0x05)
Table 7: CMS_OP_SC_FW_ERASE (0x05) Message Format
MAILBOX Offset 32-bit Word Field Type Field Description
0x00 [0] Host Request Message Message Header
31:24 Opcode (0x5)
23:0 Reserved
Notes:
1. There is no payload for this command.
Table 8: CMS_OP_SC_FW_ERASE (0x05) Worked Example
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x05000000 Write the request message header into MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS has completed
operation.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Notes:
1. Addresses used in the worked examples are offsets only.
2. Any reference to a MAILBOX Word is actually a 32-bit long word.
CMS_OP_SC_FW_SEC (0x1)
Table 9: CMS_OP_SC_FW_SEC (0x1) Message Format
MAILBOX Offset 32-bit Word Field Type Field Description
0x00 [0] Host Request Message Message Header
31:24 Opcode (0x1)
23:12 Reserved
11:0 Payload length in bytes
0x04 [1] Host Request Message Start address of the firmware section being written.
0x08 [2] Host Request Message Total length of firmware section in bytes.
0x0C-end [3:end] Host Request Message Firmware data
Notes:
1. The payload length includes the start address and the total length fields (i.e., assuming HOST_MSG_OFFSET_REG =
0x1000, a maximum of 4084 bytes of firmware data can be transferred in this message).
2. If the firmware section is too large to fit in this message, use the CMS_OP_SC_FW_DATA messages to send the
remaining chunks.
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CMS Subsystem Product Guide 17Chapter 2: Overview
Table 10: CMS_OP_SC_FW_SEC (0x1) Worked Example
Host Action Function
Peek 0x28018 Check mailbox availability by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x01000FFC Write the request message header to MAILBOX Word 0 (Opcode and payload
length).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Payload length: 4 bytes start address + 4 bytes total length + 4084 bytes firmware
data = 4092 (0xFFC).
Poke 0x29004 0x00000200 Write the start address of the firmware section to MAILBOX Word 1.
Poke 0x29008 0x00017F86 Write the total length of firmware section to MAILBOX Word 2 (in bytes).
Poke 0x2900C-0x29FFC 0xXXXXXXX Write the firmware data to the remaining 1021 MAILBOX words.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received, indicating CMS has completed the
operation.
Peek 0x28304 Confirm there are no errors in HOST_MSG_ERR_REG.
CMS_OP_SC_FW_DATA (0x02)
Table 11: CMS_OP_SC_FW_DATA (0x02) Message Format
MAILBOX Offset 32-bit Word Field Type Field Description1
0x00 [0] Host Request Message Message Header
31:24 Opcode (0x2)
23:12 Reserved
11:0 Payload length in bytes
0x04-end [1:end] Host Request Message Firmware data
Notes:
1. The entire payload may be filled with firmware data (assuming HOST_MSG_OFFSET_REG = 0x1000, a maximum of
4092 bytes of firmware data can be transferred in this message).
2. Multiple messages may be required to send a firmware section.
Table 12: CMS_OP_SC_FW_DATA (0x02) Worked Example
Host Action Function
Peek 0x28018 Check the mailbox availability by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x02000FFC Write the request message header into MAILBOX Word 0 (Opcode and payload
length).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Payload length: 4092 bytes firmware data (0xFFC).
Poke 0x29004-0x29FFC 0xXXXXXXX Write the firmware data to the remaining 1023 MAILBOX words.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received, indicating CMS has completed the
operation.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
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CMS Subsystem Product Guide 18Chapter 2: Overview
CMS_OP_SC_FW_REBOOT (0x03)
Table 13: CMS_OP_SC_FW_REBOOT (0x03) Message Format
MAILBOX Offset 32-bit Word Field Type Field Description
0x00 [0] Host Request Message Header
31:24 Opcode (0x3)
23:0 Reserved
0x04 [1] Host Request BSL Jump Address 1
Notes:
1. The BSL jump address is a fixed value of 0x201.
Table 14: CMS_OP_SC_FW_REBOOT (0x03) Worked Example
Host Action Function
Peek 0x28018 Check mailbox availability by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x03000000 Write the request message header into MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000201 Write BSL Jump Address (0x201) into MAILBOX Word 1.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS has completed the
operation.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Card Information Reporting
Card information can be requested from the satellite controller using the mailbox interface. Card
information includes:
• Card name
• Card revision
• Card serial number
• Satellite controller version
• Configuration mode
• Total power available
• Fan presence
• MAC addresses
Note: Card information messages will support one of two MAC addressing schemes depending on the
satellite controller firmware operating on the Alveo card:
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CMS Subsystem Product Guide 19Chapter 2: Overview
1. Legacy mode: Reports up to 4 MAC addresses when the factory default satellite controller firmware is
in operation.
2. Dynamic mode: A scalable solution, which reports more than 4 MAC addresses when the latest
satellite controller firmware version is in operation.
The messages required to perform this function are defined in Table 15.
Table 15: Message Header Opcodes
Opcode Name Description
0x4 CMS_OP_CARD_INFO_REQ The host requests the card information from the satellite
controller.
CMS will respond by populating the message buffer with
card information and updating the message header length
field.
CMS_OP_CARD_INFO_REQ (0x04)
Table 16: CMS_OP_CARD_INFO_REQ (0x04) Message Format
MAILBOX Offset 32-bit Word Field Type Field Description
0x00 [0] Host Request Message Message Header
CMS Response Message 31:24 Opcode (0x4)
23:12 Reserved
11:0 CMS response length in bytes
0x04-end [1:end] CMS Response Message Response payload
Card information is packed as an array of
uint8s. Each card information field is
defined as .
See Table 17 for more details.
Table 17: CMS_OP_CARD_INFO_REQ (0x04) Card Information Sensor ID
Sensor ID Name Key Length Payload
SNSR_ID_CARD_SN 0x21 Variable (n) n-1 characters ASCII Text + termination string 0x00
SNSR_ID_MAC_ADDRESS0 0x22 0x12 17 characters ASCII Text + termination string 0x00
SNSR_ID_MAC_ADDRESS1 0x23 0x12 17 characters ASCII Text + termination string 0x00
SNSR_ID_MAC_ADDRESS2 0x24 0x12 17 characters ASCII Text + termination string 0x00
SNSR_ID_MAC_ADDRESS3 0x25 0x12 17 characters ASCII Text + termination string 0x00
SNSR_ID_CARD_REV 0x26 Variable (n) n-1 characters ASCII Text + termination string 0x00
SNSR_ID_CARD_NAME 0x27 Variable (n) n-1 characters ASCII Text + termination string 0x00
SNSR_ID_SAT_VERSION 0x28 Variable (n) n-1 characters ASCII Text + termination string 0x00
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CMS Subsystem Product Guide 20Chapter 2: Overview
Table 17: CMS_OP_CARD_INFO_REQ (0x04) Card Information Sensor ID (cont'd)
Sensor ID Name Key Length Payload
SNSR_ID_TOTAL_POWER_AVAIL 0x29 0x1 0x00 = 75W
0x01 = 150W
0x02 = 225W
0x04 = 300W
SNSR_ID_FAN_PRESENCE 0x2A 0x1 ASCII Text
SNSR_ID_CONFIG_MODE 0x2B 0x1 0x00 = Slave_Serial_x1
0x01 = Slave_Select_Map_x8
0x02 = Slave_Map_x16
0x03 = Slave_Select_Map_x32
0x04 = JTag_Boundary_Scan_x1
0x05 = Master_SPI_x1
0x06 = Master_SPI_x2
0x07 = Master_SPI_x4
0x08 = Master_SPI_x8
0x09 = Master_BPI_x8
0x0a = Master_BPI_x16
0x0b = Master_Serial_x1
0x0c = Master_Select_Map_x8
0x0d = Master_Select_Map_x16
SNSR_ID_NEW_MAC_SCHEME 0x4B 0x8 Byte 1: Number of contiguous MAC addresses.
Byte 2: Reserved.
Bytes 3-8: Hex value of the first MAC address.
SNSR_ID_CAGE_TYPE_00 0x50 0x1 0x00 = QSFP/QSFP+
0x01 = DSFP
0x02 = SFP/SFP+
SNSR_ID_CAGE_TYPE_01 0x51 0x1 0x00 = QSFP/QSFP+
0x01 = DSFP
0x02 = SFP/SFP+
SNSR_ID_CAGE_TYPE_02 0x52 0x1 0x00 = QSFP/QSFP+
0x01 = DSFP
0x02 = SFP/SFP+
SNSR_ID_CAGE_TYPE_03 0x53 0x1 0x00 = QSFP/QSFP+
0x01 = DSFP
0x02 = SFP/SFP+
Table 18: CMS_OP_CARD_INFO_REQ (0x04) Worked Example
Host Action Function
Peek 0x28018 Check mailbox availability by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x04000000 Write request message header into MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message available.
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Table 18: CMS_OP_CARD_INFO_REQ (0x04) Worked Example (cont'd)
Host Action Function
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS Response is available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Peek 0x29000 Read header bits 11:0 to determine the number of bytes in CMS Response
payload.
Peek 0x29004-end Read the card information data and decode each key-length-payload field. See
Figure 6 and Figure 7 for more details.
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CMS Subsystem Product Guide 22Chapter 2: Overview
Figure 6: Card Information
Opcode Length
0x04 0x00 0x00 0x3B
Message Header
0x4c 0x41 Length=0x0d Key=0x27 270d414c56454f2055353020505100
SNSR_ID_CARD_NAME = ALVEO U50 PQ
Message
Payload 0x20 0x4f 0x45 0x56
(little endian)
0x20 0x30 0x35 0x55
Sensor ID
Key
Key=0x26 0x00 0x51 0x50 26023100 SNSR_ID_CARD_REV = 1
210d35303132313131394353504d00
Key=0x21 0x00 0x31 Length=0x02 SNSR_ID_CARD_SN = 50121119CSPM
Length
0x31 0x30 0x35 Length=0x0d
Payload 0x31 0x31 0x31 0x32
0x50 0x53 0x43 0x39
Payload
Termination Length=0x08 Key=0x4B 0x00 0x4d
4B080400000A35050FD8
SNSR_ID_NEW_MAC_SCHEME
NUM_MAC_ADDRESSES = 4
SNSR_ID_MAC_ADDRESS0 = 00:0A:35:05:0F:D8
SNSR_ID_MAC_ADDRESS1 = 00:0A:35:05:0F:D9
0x0A 0x00 0x00 0x04 SNSR_ID_MAC_ADDRESS2 = 00:0A:35:05:0F:DA
SNSR_ID_MAC_ADDRESS3 = 00:0A:35:05:0F:DB
0xD8 0x0F 0x05 0x35
Key=0x2b 0x50 Length=0x01 Key=0x2a 2a01 50 SNSR_ID_FAN_PRESENCE = P
Length=0x01 Key=0x29 0x07 Length=0x01 2b0107
SNSR_ID_CONFIG_MODE = Master_SPI_x4
290100
0x35 Length=0x04 Key=0x28 0x00 SNSR_ID_TOTAL_POWER_AVAIL = 75W
0x00 0x30 0x2e 2804352e3000
SNSR_ID_SAT_VERSION = 5.0
X25360-061521
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CMS Subsystem Product Guide 23Chapter 2: Overview
Figure 7: Legacy MAC Address Response Example
221230303a30413a33353a30363a37303a303000
0x30 0x30 Length=0x12 Key=0x22
SNSR_ID_MAC_ADDRESS0 = 00:0A:35:06:70:00
0x3a 0x41 0x30 0x3a
Message
Payload
(little endian) 0x30 0x3a 0x35 0x33
0x30 0x37 0x3a 0x36
Sensor ID Key
0x00 0x30 0x30 0x3a
231230303a30413a33353a30363a37303a303100
Length 0x30 0x30 Length=0x12 Key=0x23
SNSR_ID_MAC_ADDRESS1 = 00:0A:35:06:70:01
0x3a 0x41 0x30 0x3a
Payload
0x30 0x3a 0x35 0x33
Payload 0x30 0x37 0x3a 0x36
Termination
0x00 0x31 0x30 0x3a
241230303a30413a33353a30363a37303a303200
0x30 0x30 Length=0x12 Key=0x24
SNSR_ID_MAC_ADDRESS2 = 00:0A:35:06:70:02
0x3a 0x41 0x30 0x3a
0x30 0x3a 0x35 0x33
0x30 0x37 0x3a 0x36
0x00 0x32 0x30 0x3a
251230303a30413a33353a30363a37303a303300
0x30 0x30 Length=0x12 Key=0x25
SNSR_ID_MAC_ADDRESS3 = 00:0A:35:06:70:03
0x3a 0x41 0x30 0x3a
0x30 0x3a 0x35 0x33
0x30 0x37 0x3a 0x36
0x00 0x33 0x30 0x3a
X25359-061121
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CMS Subsystem Product Guide 24Chapter 2: Overview
Network Plug-in Module Management
The CMS IP supports management of network plug-in modules via the mailbox, as specified in
the following table.
Table 19: CMS IP Network Plug-in Module Support Per Card
Network Plug-in Module Type U200/U250 U280 U50 U55 SN1000 X3522
QSFP ✓ ✓ ✓ ✓ ✓
DSFP ✓
SFP+ ✓
The mailbox interface supports the following network plug-in module management features:
• I2C access for diagnostics and control
• Low speed I/O status and control
The messages required to perform these functions are defined in the following table.
Table 20: Message Header Opcodes
Opcode Name Description
0xD CMS_OP_READ_MODULE_LOW_SPEED_IO Host request to read network plug-in module low speed
I/O.
0xE CMS_OP_WRITE_MODULE_LOW_SPEED_IO Host request to write network plug-in module low speed
I/O.
0xB CMS_OP_BLOCK_READ_MODULE_I2C Host request to block read network plug-in module I2C
information.
0xF CMS_OP_BYTE_READ_MODULE_I2C Host request to byte read network plug-in module I2C
information.
0x10 CMS_OP_BYTE_WRITE_MODULE_I2C Host request to byte write network plug-in module I2C
information.
CMS_OP_READ_MODULE_LOW_SPEED_IO (0x0D)
Table 21: CMS_OP_READ_MODULE_LOW_SPEED_IO (0x0D) Message Format
MAILBOX
32-bit Word Field Type Field Description
Offset
0x00 [0] Host Request Message Message Header
31:24 Opcode (0xD)
23:0 Reserved
0x04 [1] Host Request Message Cage Select (0-1)
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Table 21: CMS_OP_READ_MODULE_LOW_SPEED_IO (0x0D) Message Format (cont'd)
MAILBOX
32-bit Word Field Type Field Description
Offset
0x08 [2] CMS Response Message Low Speed I/O Read Data
QSFP Module
31-5: Reserved
4: QSFP_INT_L (0: Interrupt Set, 1: Interrupt Clear)
3: QSFP_MODPRS_L (0: Module Present, 1: Module
not Present)
2: QSFP_MODSEL_L (0: Module Selected, 1:
Module not Selected)
1: QSFP_LPMODE (0: High Power Mode, 1: Low
Power Mode)
0: QSFP_RESET_L (0: Reset Active, 1: Reset Clear)
DSFP Module
31-5: Reserved
4: DSFP_INT (0: Interrupt Clear, 1: Interrupt Set)
3: DSFP_PRS (0: Module not Present, 1: Module
Present)
2: Reserved
1: DSFP_LPW (0: High Power Mode, 1: Low Power
Mode)
0: DSFP_RST (0: Reset Clear, 1: Reset Active)
SFP+ Module
31-4: Reserved
3: SFP_PRS (0: Module not Present, 1: Module
Present)
2-0: Reserved
Table 22: CMS_OP_READ_MODULE_LOW_SPEED_IO (0x0D) Worked Example
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x0D000000 Write the request message header into MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Select Cage 0
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS Response is available.
Peek 0x28304 Confirm there are no errors in HOST_MSG_ERR_REG.
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Table 22: CMS_OP_READ_MODULE_LOW_SPEED_IO (0x0D) Worked Example (cont'd)
Host Action Function
Peek 0x29008 Read low speed I/O read data and decode according to module type.
Example 1 : QSFP module read data 0x11
• Bit 4 - QSFP_INT_L = 1 - Interrupt Clear
• Bit 3 - QSFP_MODPRS_L = 0 - Module Present
• Bit 2 - QSFP_MODSEL_L = 0 - Module Selected
• Bit 1 - QSFP_LPMODE = 0 - High Power Mode
• Bit 0 - QSFP_RESET_L = 1 - Reset Clear
Example 2 : DSFP module read data 0x0A
• Bit 4 - DSFP_INT = 0 - Interrupt Clear
• Bit 3 - DSFP_PRS = 1 - Module Present
• Bit 1 - DSFP_LPW = 1 - Low Power Mode
• Bit 0 - DSFP_RST = 0 - Reset Clear
Example 3 : SFP+ module read data 0x08
• Bit 3 - SFP_PRS = 1 - Module Present
CMS_OP_WRITE_MODULE_LOW_SPEED_IO (0x0E)
Table 23: CMS_OP_WRITE_MODULE_LOW_SPEED_IO (0x0E) Message Format
MAILBOX
32-bit Word Field Type Field Description
Offset
0x00 [0] Host Request Message Message Header
31:24 Opcode (0xE)
23:0 Reserved
0x04 [1] Host Request Message Cage Select (0-1)
0x08 [2] Host Request Message Low Speed I/O Write Data 1, 2
QSFP Module
31-2: Reserved
1: QSFP_LPMODE (0: High Power Mode, 1: Low
Power Mode)
0: QSFP_RESET_L (0: Reset Active, 1: Reset Clear)
DSFP Module
Low Speed I/O Read Data - DSFP Module
31-2: Reserved
1: DSFP_LPW (0: High Power Mode, 1: Low Power
Mode)
0: DSFP_RST (0: Reset Clear, 1: Reset Active)
SFP+ Module
Low Speed I/O Read Data - SFP+ Module
31-0: Reserved
Notes:
1. All bits are written together. Use a read-modify-write sequence to update required bit(s).
2. Writing 0 to QSFP_RESET_L will trigger a module reset.
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Table 24: CMS_OP_WRITE_MODULE_LOW_SPEED_IO (0x0E) Worked Example - QSFP
Module
Host Action Function
Peek 0x28018 Check availability of the Mailbox by confirming CONTROL_REG[5] is 0
Poke 0x29000 0x0E000000 Write Request Message Header into MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Select Cage 0
Poke 0x29008 0x00000000 Set QSFP Low speed Write Data. Write 0 to QSFP_RESET_L to trigger a QSFP
module reset.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS has completed write
operation.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Table 25: CMS_OP_WRITE_MODULE_LOW_SPEED_IO (0x0E) Worked Example - DSFP
Module
Host Action Function
Peek 0x28018 Check availability of the Mailbox by confirming CONTROL_REG[5] is 0
Poke 0x29000 0x0E000000 Write Request Message Header into MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000001 Select Cage 1
Poke 0x29008 0x00000001 Set DSFP Low speed Write Data. Write 1 to DSFP_RST to hold DSFP module in
reset.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS has completed write
operation.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
CMS_OP_BLOCK_READ_MODULE_I2C (0xB)
Table 26: CMS_OP_BLOCK_READ_MODULE_I2C (0xB) Message Format
MAILBOX
32-bit Word Field Type Field Description
Offset
0x00 [0] Host Request Message Message Header
31:24 Opcode (0xB)
23:0 Reserved
0x04 [1] Host Request Message Cage Select (0–1)
0x08 [2] Host Request Message Page Select (0–255)
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Table 26: CMS_OP_BLOCK_READ_MODULE_I2C (0xB) Message Format (cont'd)
MAILBOX
32-bit Word Field Type Field Description
Offset
0x0C [3] Host Request Message Extended I2C Addressing
31:23 Reserved
22:18 CMIS Bank (0-31)
17 CMIS Bank Field Valid (0: False, 1:True)
16 I2C Address Field (0: 0xA0, 1: 0xA2) 1
15:1 Reserved
0 Lower/Upper Page Select (0: Lower, 1: Upper)
0x10 [4] CMS Response Message Response Size (in bytes)
0x14-end [5:end] CMS Response Message Response Payload (little endian)
31:24 Module I2C read data byte n+3
23:16 Module I2C read data byte n+2
15:8 Module I2C read data byte n+1
7:0 Module I2C read data byte n
Notes:
1. I2C address field 0xA2 only supported in SFP+ modules.
Table 27: CMS_OP_BLOCK_READ_MODULE_I2C (0xB) Worked Example - QSFP Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x0B000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Select cage 0 via MAILBOX Word 1.
Poke 0x29008 0x00000003 Select page 3 via MAILBOX Word 2.
Poke 0x2900C 0x00000001 Select the upper page via MAILBOX Word 3.
Note: CMIS Bank, CMIS Bank Valid and I2C Address fields should all be set to 0x0
as they are unused in QSFP mode.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Peek 0x29010 Read the number of bytes in the CMS Response payload.
Peek 0x29014-end Read module I2C read data from MAILBOX Word 5 until the end.
Table 28: CMS_OP_BLOCK_READ_MODULE_I2C (0xB) Worked Example - DSFP Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x0B000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Select cage 0 via MAILBOX Word 1.
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Table 28: CMS_OP_BLOCK_READ_MODULE_I2C (0xB) Worked Example - DSFP Module
(cont'd)
Host Action Function
Poke 0x29008 0x00000000 Select page 0 via MAILBOX Word 2.
Poke 0x2900C 0x00020000 Select the lower page of CMIS bank 0 via MAILBOX Word 3.
Note: I2C Address field should be set to 0x0 as it is unused in DSFP mode.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Peek 0x29010 Read the number of bytes in the CMS Response payload.
Peek 0x29014-end Read module I2C read data from MAILBOX Word 5 until the end.
Table 29: CMS_OP_BLOCK_READ_MODULE_I2C (0xB) Worked Example - SFP+ Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x0B000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000001 Select cage 1 via MAILBOX Word 1.
Poke 0x29008 0x00000000 Select page 0 via MAILBOX Word 2.
Poke 0x2900C 0x00010000 Select the lower page of I2C Address field 0xA2 via MAILBOX Word 3.
Note: CMIS Bank and CMIS Bank Valid fields should be set to 0x0 as they are
unused in SFP+ mode.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Peek 0x29010 Read the number of bytes in the CMS Response payload.
Peek 0x29014-end Read module I2C read data from MAILBOX Word 5 until the end.
CMS_OP_BYTE_READ_MODULE_I2C (0xF)
Table 30: CMS_OP_BYTE_READ_MODULE_I2C (0xF) Message Format
MAILBOX
32-bit Word Field Type Field Description
Offset
0x00 [0] Host Request Message Message Header
31:24 Opcode (0xF)
23:0 Reserved
0x04 [1] Host Request Message Cage Select (0–1)
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Table 30: CMS_OP_BYTE_READ_MODULE_I2C (0xF) Message Format (cont'd)
MAILBOX
32-bit Word Field Type Field Description
Offset
0x08 [2] Host Request Message Page Select (0–255)
0x0C [3] Host Request Message Extended I2C Addressing
31:23 Reserved
22:18 CMIS Bank (0-31)
17 CMIS Bank Field Valid (0: False, 1:True)
16 I2C Address Field (0: 0xA0, 1: 0xA2) (2)
15:1 Reserved
0 Lower/Upper Page Select (0: Lower, 1: Upper)
0x10 [4] Host Request Message Byte Offset (0-255)1
0x14 [5] CMS Response Message Response Payload
31:8 Reserved
7:0 Module I2C read data byte
Notes:
1. 'Byte Offset' configuration should be consistent with 'Lower/Upper Page Select' configuration. For example, when
accessing byte offsets 0-127 the lower page should be selected; when accessing bytes 128-255 the upper page should
be selected.
2. I2C address field 0xA2 only supported in SFP+ modules.
Table 31: CMS_OP_BYTE_READ_MODULE_I2C (0xF) Worked Example - QSFP Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x0F000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Select cage 0 via MAILBOX Word 1.
Poke 0x29008 0x00000003 Select page 3 via MAILBOX Word 2.
Poke 0x2900C 0x00000001 Select the upper page via MAILBOX Word 3.
Note: CMIS Bank, CMIS Bank Valid and I2C Address fields should all be set to 0x0
as they are unused in QSFP mode.
Poke 0x29010 0x000000FF Select Byte Offset 255 via MAILBOX Word 4.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Peek 0x29014 Read module I2C read data byte from MAILBOX Word 5.
Table 32: CMS_OP_BYTE_READ_MODULE_I2C (0xF) Worked Example - DSFP Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
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Table 32: CMS_OP_BYTE_READ_MODULE_I2C (0xF) Worked Example - DSFP Module
(cont'd)
Host Action Function
Poke 0x29000 0x0F000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000001 Select cage 1 via MAILBOX Word 1.
Poke 0x29008 0x00000000 Select page 0 via MAILBOX Word 2.
Poke 0x2900C 0x00020000 Select the lower page of CMIS bank 0 via MAILBOX Word 3.
Note: I2C Address field should be set to 0x0 as it is unused in DSFP mode.
Poke 0x29010 0x0000007F Select Byte Offset 127 via MAILBOX Word 4.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Peek 0x29014 Read module I2C read data byte from MAILBOX Word 5.
Table 33: CMS_OP_BYTE_READ_MODULE_I2C (0xF) Worked Example - SFP+ Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x0F000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Select cage 0 via MAILBOX Word 1.
Poke 0x29008 0x00000000 Select page 0 via MAILBOX Word 2.
Poke 0x2900C 0x00000000 Select the lower page of I2C Address field 0xA0 via MAILBOX Word 3.
Note: CMIS Bank and CMIS Bank Valid fields should be set to 0x0 as they are
unused in SFP+ mode.
Poke 0x29010 0x00000000 Select Byte Offset 0 via MAILBOX Word 4.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Peek 0x29014 Read module I2C read data byte from MAILBOX Word 5.
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CMS_OP_BYTE_WRITE_MODULE_I2C (0x10)
Table 34: CMS_OP_BYTE_WRITE_MODULE_I2C (0x10) Message Format
MAILBOX
32-bit Word Field Type Field Description
Offset
0x00 [0] Host Request Message Message Header
31:24 Opcode (0x10)
23:0 Reserved
0x04 [1] Host Request Message Cage Select (0–1)
0x08 [2] Host Request Message Page Select (0–255)
0x0C [3] Host Request Message Extended I2C Addressing
31:23 Reserved
22:18 CMIS Bank (0-31)
17 CMIS Bank Field Valid (0: False, 1:True)
16 I2C Address Field (0: 0xA0, 1: 0xA2) (2)
15:1 Reserved
0 Lower/Upper Page Select (0: Lower, 1: Upper)
0x10 [4] Host Request Message Byte Offset (0-255) 1
0x14 [5] Host Request Message Request Payload
31:8 Reserved
7:0 Module I2C write data byte
Notes:
1. 'Byte Offset' configuration should be consistent with 'Lower/Upper Page Select' configuration. For example, when
accessing byte offsets 0-127 the lower page should be selected; when accessing bytes 128-255 the upper page should
be selected.
2. I2C address field 0xA2 only supported in SFP+ modules.
Table 35: CMS_OP_BYTE_WRITE_MODULE_I2C (0x10) Worked Example - QSFP Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x10000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Select cage 0 via MAILBOX Word 1.
Poke 0x29008 0x00000003 Select page 3 via MAILBOX Word 2.
Poke 0x2900C 0x00000001 Select the upper page via MAILBOX Word 3.
Note: CMIS Bank, CMIS Bank Valid and I2C Address fields should all be set to 0x0
as they are unused in QSFP mode.
Poke 0x29010 0x000000FF Select Byte Offset 255 via MAILBOX Word 4.
Poke 0x29014 0x00000080 Write module I2C data byte to MAILBOX Word 5.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
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CMS Subsystem Product Guide 33Chapter 2: Overview
Table 36: CMS_OP_BYTE_WRITE_MODULE_I2C (0x10) Worked Example - DSFP Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x10000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000001 Select cage 1 via MAILBOX Word 1.
Poke 0x29008 0x00000000 Select page 0 via MAILBOX Word 2.
Poke 0x2900C 0x00020000 Select the lower page of CMIS bank 0 via MAILBOX Word 3.
Note: I2C Address field should be set to 0x0 as it is unused in DSFP mode.
Poke 0x29010 0x0000007F Select Byte Offset 127 via MAILBOX Word 4.
Poke 0x29014 0x00000001 Write module I2C data byte to MAILBOX Word 5.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
Table 37: CMS_OP_BYTE_WRITE_MODULE_I2C (0x10) Worked Example - SFP+ Module
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x10000000 Write the request message header to MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000001 Select cage 1 via MAILBOX Word 1.
Poke 0x29008 0x00000000 Select page 0 via MAILBOX Word 2.
Poke 0x2900C 0x00000000 Select the lower page of I2C Address field 0xA0 via MAILBOX Word 3.
Note: CMIS Bank and CMIS Bank Valid fields should be set to 0x0 as they are
unused in SFP+ mode.
Poke 0x29010 0x0000007F Select Byte Offset 127 via MAILBOX Word 4.
Poke 0x29014 0x00000001 Write module I2C data byte to MAILBOX Word 5.
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating the CMS response is
available.
Peek 0x28304 Confirm no errors in HOST_MSG_ERR_REG.
SN1000 SoC Management
The mailbox interface supports commands for managing the external System on Chip (SoC)
device on SN1000 Cards:
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CMS Subsystem Product Guide 34Chapter 2: Overview
• SoC Status Reporting
○ SoC State
○ SoC Type
○ SoC Firmware Versions
• SoC Control
○ Reset SoC Device
○ Enable SoC Device
○ Disable SoC Device
The messages required to perform these functions are defined in the following table.
Table 38: Message Header Opcodes
Opcode Name Description
0x11 CMS_OP_READ_SOC_STATUS Host request to read SoC Status Information
0x12 CMS_OP_WRITE_SOC_CONTROL Host request to write SoC Control Information
CMS_OP_READ_SOC_STATUS (0x11)
Table 39: CMS_OP_READ_SOC_STATUS (0x11) Message Format
MAILBOX
32-bit Word Field Type Field Description
Offset
0x00 [0] Host Request Message Message Header
31:24 Opcode (0x11)
23:0 Reserved
0x04 [1] Host Request Message SoC Status Opcode
31:8 Reserved
7:0 SoC Status Opcode (0: System Status, 1:
Firmware Versions)
0x08 [2] Host Request Message System Status Response
31:6 Reserved
5 OS Recovery Required (0: False, 1: True)
4 SoC Enable Status (0: Disabled, 1: Enabled)
3:0 SoC State (0: Power-On, 1: U-Boot, 2: OS
Starting, 3: OS Running, 4: OS Maintenance)
Firmware Versions Response
31:8 Reserved
7:0 Number of firmware versions reported
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CMS Subsystem Product Guide 35Chapter 2: Overview
Table 39: CMS_OP_READ_SOC_STATUS (0x11) Message Format (cont'd)
MAILBOX
32-bit Word Field Type Field Description
Offset
0x0C [3] CMS Response Message System Status Response
31:8 Reserved
7:0 SoC Type (0: Undefined, 1: LX2162A)
Firmware Versions Response
31:8 Reserved
7:0 Version ID #1 (0: Boot Program, 1: U-Boot, 2:
OS, 3: OS Maintenance)
0x10 [4] CMS Response Message Firmware Versions Response
31:16 Minor Version #1
15:0 Major Version #1
0x14 [5] CMS Response Message Firmware Versions Response
31:16 Build Version #1
15:0 Patch Version #1
0x18 [6] CMS Response Message Firmware Versions Response
31:8 Reserved
7:0 Version ID #2 (0: Boot Program, 1: U-Boot, 2:
OS, 3: OS Maintenance)
0x1C [7] CMS Response Message Firmware Versions Response
31:16 Minor Version #2
15:0 Major Version #2
0x20 [8] CMS Response Message Firmware Versions Response
31:16 Build Version #2
15:0 Patch Version #2
0x24-end [9-end] CMS Response Message Firmware Versions Response
Version ID, Major, Minor, Patch and Build
information will be reported for remaining
firmware versions in same format as defined in
words 6-8 above.
Table 40: CMS_OP_READ_SOC_STATUS (0x11) Worked Example - System Status
Host Action Function
Peek 0x28018 Check availability of the mailbox by confirming CONTROL_REG[5] is 0.
Poke 0x29000 0x11000000 Write the request message header into MAILBOX Word 0 (Opcode).
Assumes HOST_MSG_OFFSET_REG = 0x1000.
Poke 0x29004 0x00000000 Set SoC Status Opcode to 0x0 System Status
Poke 0x28018 0x20 Set CONTROL_REG[5] to 1 to indicate a new request message is available.
Peek 0x28018 Poll CONTROL_REG bit 5 until ‘0’ is received indicating CMS Response is available.
Peek 0x28304 Confirm there are no errors in HOST_MSG_ERR_REG.
Peek 0x29008 Read 1st word of SoC System Status response data to determine SoC Status.
e.g 0x00000011 : SoC State = U-Boot, SoC Enable Status = Enabled
Peek 0x2900C Read 2nd word of SoC System Status response data to determine SoC type.
e.g. 0x00000001 : SoC Type = LX2162A
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