Area-efficient Ramp Signal-based Column Driving Technique for AMOLED Panels - JSTS
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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.4, AUGUST, 2019 ISSN(Print) 1598-1657
https://doi.org/10.5573/JSTS.2019.19.4.347 ISSN(Online) 2233-4866
Area-efficient Ramp Signal-based Column Driving
Technique for AMOLED Panels
Tai-Ji An1, Moon-Sang Hwang2, Won-Jun Choe2, Jun-Sang Park3,
Gil-Cho Ahn3, and Seung-Hoon Lee3
Abstract—This work proposes a ramp signal-based I. INTRODUCTION
column driving technique to maximize the area
efficiency of the column driver integrated circuit (IC) Recently, high-resolution displays such as wide quad
for high-resolution active-matrix organic light extended graphics array (WQXGA) and ultra-high
emitting diodes (AMOLED) panels. The proposed definition (UHD) panels have been widely employed in
column driving technique replaces the 2n reference mobile devices such as smart phones and tablet PC’s.
voltages coming from the conventional n-bit resistor Demand for active-matrix organic light emitting diodes
digital-to-analog converters (RDAC) with a single (AMOLED) to maintain low power consumption at high-
ramp signal, thereby reducing the area of the column resolution has also increased. With the rapidly increasing
driver IC by 44.3%. A weighted two-step demand for high-resolution panels including AMOLED
interpolation structure, composed of the first-stage 6- panels, there have been a growing number of studies
bit ramp signal and the second-stage 2-bit amplifier conducted on the development of improved multi-
DAC, reduces the required operation speed of the channel column driver integrated circuits (IC's). For
ramp signal under a limited 1-horizontal (1-H) time, those column driver IC’s, an 8- to 10-bit digital-to-analog
while processing 8-bit image signals. The converter (DAC) is required to convert digital image
performance of the proposed column driving signals into analog signals. In the conventional column
technique is verified with a 96-channel prototype IC driver IC’s, a resistor DAC (RDAC) based on global
fabricated in a 0.18 μm CMOS process. The deviation resistor strings, typically demonstrating dependable
of voltage output (DVO) of the prototype IC are output uniformity among channels, has been commonly
within ±6 mV, and the unit channel area is 4200 μm2. used [1-3]. However, in the case of RDAC’s, it has been
difficult to efficiently reduce the area of the column
Index Terms—Active-matrix organic light emitting driver IC, considering that 2n reference voltages and 2n+1-
diodes (AMOLED), column driver integrated circuit 2 analog switches are required. Two-step interpolation
(IC), digital-to-analog converter (DAC), ramp signal, structures, where the RDAC is employed in the first
two-step interpolation. stage, have been previously developed [4-10] and have
been found to both increase area efficiency and maintain
the channel uniformity among channels. However, since
the first-stage RDAC commonly should process more
than 6 bits in order to maintain uniformity among the
Manuscript received Feb. 8, 2019; accepted Aug. 5, 2019 channels, it is not easy to reduce the area.
1
Samsung Electronics Company, Limited, Hwaseong 18448, Korea
2
Samsung Display Company, Limited, Yong-in 17113, Korea As an example, an UHD display system with a frame
3
Department of Electronic Engineering, Sogang University, Seoul 04107, rate of 60 Hz is shown in Fig. 1, where six 960-channel
Korea
E-mail : hoonlee@sogang.ac.kr
column driver IC’s are used with the 2:1 DEMUX348 TAI-JI AN et al : AREA-EFFICIENT RAMP SIGNAL-BASED COLUMN DRIVING TECHNIQUE FOR AMOLED PANELS
Fig. 1. Common UHD-Resolution AMOLED Display System.
function. In general, since a single DAC is used per unit
channel in the column driver IC, it is difficult to reduce Fig. 2. Conventional k-Channel Column Driver IC Based on the
Channel RDAC Structure.
the chip area of the column driver IC in the high-
resolution display panel. This paper is organized as follows. Section Ⅱ details
In order to increase the area efficiency of the RDAC- the proposed ramp signal-based column driving
based column driver IC, a time-shared DAC architecture
technique and its operating principle. Section Ⅲ
in which a single DAC is shared among multiple
summarizes the proposed circuit design techniques. The
channels was proposed in [11]. However, since the single
fabricated and measured results of the 96-channel test
DAC is shared among multiple channels during the
chip are summarized in Section Ⅳ and the conclusion is
limited 1-horizontal (1-H) time, a high operation speed is
given in Section Ⅴ.
needed in the time-shared DAC structure. In addition, to
improve the settling behavior of the global reference
voltages within the wide width of the column driver IC, a II. ARCHITECTURE
large amount of power consumption is required. Since
the 1-H time is also shared among the shared DAC and 1. Concept of the Proposed Ramp Signal-based
the output amplifiers, it is not easy to optimize the power Column Driving Technique
consumption of the column driver IC.
The effective 1-H time of the column driver IC used in The conventional column driver IC’s in AMOLED
60 Hz/frame UHD AMOLED panels, which are currently panels commonly use a channel RDAC structure based
in high demand, is approximately 3.5 μs. Compared to on global reference voltages as shown in Fig. 2. As the
the 15.4 μs of the 60 Hz/frame full high definition (FHD) resolution increases, the number of the global reference
panels, the operation speed of the aforementioned voltage lines and channel analog switches also increases
AMOLED panels is approximately four times faster. exponentially.
This paper proposes a ramp signal-based column Two-step interpolation structures have been employed
driving technique, which is able to reduce the area of the commonly to reduce the area of the high-resolution
column driver IC of 60 Hz/frame UHD AMOLED panels. RDAC, where the first-stage RDAC processes at least 6
Using the single-line ramp signal, which varies bits to obtain uniformity among the channels. In
consecutively in time, each channel is able to sample and AMOLED panels, since each RGB pixel is distinct from
hold an analog voltage corresponding to the digital input. all others, the output characteristics of each global
At this time, to reduce the required operation speed of the reference voltage have to be controlled individually. As a
ramp signal within the limited 1-H time, a two-step result, 3´26 global reference voltage lines are needed in
interpolation structure composed of a first-stage 6-bit the column driver IC for the AMOLED panel [12]. In
ramp signal and a second-stage 2-bit amplifier DAC addition, n level shifters of each channel, which occupy a
(amp DAC) is employed. large area, limit the realization of the small-area columnJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.4, AUGUST, 2019 349
Table 1. Channel Height Comparison of the Channel RDAC-
Based Driver IC and Ramp Signal-Based Driver IC
RDAC-based Ramp-based
Column Driver IC Column Driver IC
Holding Latches 26 μm 26 μm
Level Shifters 60 μm 10 μm
Sampling Control Not Used 47 μm
2n-to-1 MUX (RGB) 384 μm Not Used
Ramp Lines (RGB) Not Used 20 μm
Sampling Circuit Not Used 90 μm
Output Amplifier 155 μm 155 μm
Total 625 μm 348 μm
Fig. 3. Proposed k-Channel Ramp Signal-Based Column Driver
IC.
driver IC.
In this paper, a ramp signal-based column driving
technique is proposed to reduce the area of the column
driver IC which increases exponentially with the
resolution. The k-channel column driver IC is described
Fig. 4. Operation Timing of the Proposed Ramp Signal-Based
in Fig. 3, where the proposed column driving technique
Column Driving Technique with an Example of 6-bit
is applied. The ramp signal-based column driver IC Operation.
employs only a single analog ramp signal and n-bit
binary count signals which are synchronized with the The channel height comparison of the channel RDAC-
main clock (QCK) and which change consecutively to all based driver IC and the ramp signal-based driver IC is
channels simultaneously. As a result, the area of the summarized in Table 1. For a fair comparison, a two-step
column driver IC is 44.3% reduced. Moreover, by interpolation architecture, which uses a 6-bit RDAC at
reducing the number of level shifters for each channel the first stage, is employed in both column driver IC’s.
from n to 1, the area can be further reduced. The proposed ramp signal-based column driver IC shows
The proposed k-channel ramp signal-based column a 44.3% area reduction effect, and it can maximize the
driver IC is composed of an n-bit binary counter, a ramp area efficiency as the resolution of the driver IC increases.
signal generator, and k unit channel circuits. For the
RGB-independent gamma characteristic of the 2. Timing of the Proposed Ramp Signal-based Column
AMOLED panel, three ramp signal generators should be Driving Technique
used. Each unit channel circuit consists of holding
latches, a sampling control circuit, a level shifter, a The 6-bit operation and timing examples of the
sampling capacitor, and an output amplifier. In the proposed ramp signal-based column driving technique
proposed column driver IC, the 2n corresponding analog are described in Fig. 4 in detail. During the T1 period,
voltages are expressed as a ramp signal, changing the ramp signal (Vr) and the binary count signals (DCO)
consecutively, while delivered to all channels. are all reset. Then, Vr and DCO increase by 1 LSB
Simultaneously, each channel uses the digital circuit consecutively synchronized with QCK and are delivered
composed of low-voltage devices to hold the analog to all channels during the T2 period. The sampling
voltage corresponding to the timing, reducing switching control circuit of each channel compares two digital
power consumption and active die area compared to the inputs, DI and DCO, and changes the sampling signal (QS)
conventional column driver IC using high-voltage from ‘high’ to ‘low’ when the two digital codes are
MUX’s. identical. The sampling capacitor at the input node of the350 TAI-JI AN et al : AREA-EFFICIENT RAMP SIGNAL-BASED COLUMN DRIVING TECHNIQUE FOR AMOLED PANELS
output amplifier tracks the ramp signal from the start of
the T2 period. When QS becomes ‘low’, the sampling
switch turns off and the sampling capacitor holds the
corresponding analog voltage.
However, in the proposed column driving architecture,
the ramp signal has 2n operation periods to represent n-
bit image signals in the limited 1-H time and should be
delivered to all channels within an operation period with (a)
the required settling accuracy. In the following Section
Ⅲ, the design techniques to overcome the limitations are
discussed.
III. CIRCUIT IMPLEMENTATION
1. Single-channel Architecture with Two-step (b)
Interpolation Fig. 5. Two-Step Interpolation for a Single Channel (a)
Conventional, (b) Proposed Interpolation Schemes.
The proposed column driving technique employs a
single ramp signal and n–bit binary count signal lines capacitance (CP) [7, 8]. The amplifier interpolation,
across all channels. Although the area of the column which separates the input node of the output amplifier, is
driver IC can be significantly reduced, 2n operation most commonly used in commercial products and has
periods depending on the resolution are still required for good linearity and channel uniformity [9, 10]. Therefore,
the ramp signal. Thus, to express 8-bit signals with 256 this work proposes an interpolation structure which
gray scales, the ramp signal must be changed combines amplifier interpolation and sampling timing
consecutively for a total of 256 periods. For example, if control of the ramp signal as shown in Fig. 5(b).
the 1-H time is 3.5 μs, the ramp signal should be, taking The unit channel architecture of the proposed ramp
into account the settlement margin of the output signal-based column driver IC is described in Fig. 6. In
amplifier (= 1.0 μs), settled within approximately 10 ns this work, an 8-bit image signal is processed by the 6-bit
with the required accuracy. In the case of a wide multi- ramp signal and the 2-bit amp DAC. The timing control
channel column driver IC, a large amount of power is circuit is implemented with simple digital logic circuits
required to settle the ramp signal before it can be operating at a low supply voltage. The unit channel
delivered to all channels within the required period of circuit receives the 6-bit digital count signal (DCO), the
time which may be as short as 10 ns. Considering these ramp signal (Vr), the 8-bit digital input (DI), and the main
requirements in the proposed column driving technique, clock signal (QCK). The holding latches store DI during
the proper two-step interpolation structure needs to be the 1-H period. The 6-bit digital comparator compares
employed to reduce the operation periods of the ramp DCO with 6 MSB’s of DI and decides its output of QH.
signal. When two digital codes are identical, QH changes from
In the conventional two-step interpolation structures, ‘high’ to ‘low’. The 2-bit interpolation control circuit
two adjacent voltages to the first-stage DAC, Vh and Vl, receives QH and 2 LSB’s of DI, and then generates three
are selected and the differential voltage between the two sampling signals, QS0, QS1, and QS2, to control the three
voltages is divided in the second stage. The three most separated sampling capacitors and sampling switches in
common two-step interpolation structures are shown in the input node of the output amplifier.
Fig. 5(a). The resistor interpolation can lead to channel The timing of the sampling and interpolation signals
mismatch due to errors in the current supplied to the (QS1~3), depending on 2 LSB’s of DI, is desribed in the
second resistor string [4-6]. The capacitor interpolation right top table of Fig. 6. Each sampling capacitor samples
may result in nonlinear errors due to parasitic Vr(n) or Vr(n+1) depending on 2 LSB’s of DI. The outputJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.4, AUGUST, 2019 351
(a)
Fig. 6. Two-Step Interpolated Single Channel for the Proposed
8-bit Column Driver IC.
Table 2. Inputs and Outputs of the 2-bit DAC Embedded
Output Amplifier (b)
DI in0 in1 in2 Vo
Fig. 8. Ramp-Signal Buffer Design for the 960-Channel
00 Vr(n) Vr(n) Vr(n) Vr(n)
Column Driver IC (a) RC Parasitic of the Ramp-Signal Buffer,
01 Vr(n) Vr(n+1) Vr(n) (3Vr(n)+1Vr(n+1))/4 (b) the Required Settling Accuracy Estimation.
10 Vr(n) Vr(n) Vr(n+1) (2Vr(n)+2Vr(n+1))/4
11 Vr(n) Vr(n+1) Vr(n+1) (1Vr(n)+3Vr(n+1))/4 commonly have a large width of over 10 mm. The global
reference voltage circuit of the RDAC tends to be located
at the chip center. At this time, the global reference
voltage circuit needs to deliver the reference voltage
uniformly as far as the outermost channel within the
limited 1–H time. Meanwhile, the 1-H time of the 60
Hz/frame UHD panel is 10 μs. If a 2:1 DEMUX function
is used, the effective 1-H time of the unit column driver
IC should be 3.5 μs [17]. Assuming a settling margin of
the output amplifier is 1 μs, the ramp signal of the
proposed column driving technique is processed within
the time period as given by dividing 2.5 μs by 64 periods.
Fig. 7. Output Amplifier for backend 2-bit Interpolation [16]. As a result, the unit period of the ramp signal is
approximately 40 ns. When the ramp-signal buffer is
amplifier then divides the gap between the two sampled located at the chip center, its parasitic resistance and
voltages and delivers the final output voltage to the capacitance in the 960-channel column driver IC are
AMOLED panel. The sampled voltages of each input modeled as Fig. 8(a).
node and the final output voltage of the output amplifier, In this work, including all parasitic elements, such as
based on 2 LSB’s of DI, are summarized in Table 2. routing metals, device parasitics, and sampling capacitors,
The circuit diagram of the output amplifier is shown in the parasitic resistance and capacitance of each channel
Fig. 7, where the 2 LSB’s interpolation function is added. are estimated as 1.13 Ω and 318 fF, respectively, when
The employed output amplifier has a class-AB output each channel uses three sampling capacitors of 100 fF.
stage and divides the three input nodes to generate the Considering the distance from the ramp-signal buffer to
output voltages between the sampled Vr(n) and Vr(n+1) the channels located at the chip center (CH478 and
depending on 2 LSBs [13-16]. CH481), the additional parasitic resistance and
capacitance of 100 Ω and 1 pF, respectively, are also
2. Design Considerations of the Ramp-signal Buffer added. At this time, the time constant from the ramp-
signal buffer to the outermost channel (CH1) is
Multi-channel column driver IC’s based on the RDAC approximately 9 ns. When the output voltage range is 4352 TAI-JI AN et al : AREA-EFFICIENT RAMP SIGNAL-BASED COLUMN DRIVING TECHNIQUE FOR AMOLED PANELS
Table 3. Simulated AC Performance of the Ramp-Signal
Buffer
SS, 100 °C TT, 25 °C TT, -40 °C
DC Gain 95 dB 104 dB 106 dB
Bandwidth 20.9 MHz 28.4 MHz 36 MHz
Phase Margin 61.9° 65.9° 69.3°
Settling Time 37.3 ns 36.3 ns 35.4 ns
RMS Current 1.13 mA 1.17 mA 1.24 mA
(a)
V, the one-step voltage (Vstep) of the 6-bit ramp signal is
62.5 mV as shown in Fig. 8(b). If the voltage accuracy
required to the final output of the column driver IC is ±2
mV, the ramp signal delivered to the outermost channel
has to be settled to 3.2 % of the target voltage, which is
approximately 5-bit resolution, within 40 ns. Under this
condition, the required small signal bandwidth (f-3dB) of
the ramp-signal buffer calculated with Eq. (1) is
approximately 18.4 MHz. In Eq. (1), n is the required
(b)
resolution of the output and ts is the settling time. The
width of the routing metal needs to be determined such Fig. 9. Simulated Waveform of the Ramp Signals with the 960-
Channel RC Parasitic (a) Settling Behavior, (b) Channel
that 4τ of the RC time constant of the ramp signal from Variations.
the chip center to outermost channels is within 40 ns.
Table 4. Simulated DVO and AVO in the 960-Channel
n ´ ln 2 Environment
f -3dB = (1)
2p ´ ts SS, 100 °C TT, 25 °C TT, -40 °C
DVO 0.10 mV 0.32 mV 0.40 mV
The designed AC performance of the ramp-signal AVO 1.77 mV 1.52 mV 1.37 mV
buffer is summarized in Table 3. As a result of this
design, when the required bandwidth is specified under signals, the deviation of voltage output (DVO: deviation
the slowest operation condition (SS, 100 °C), the current of voltage output) among the channels within a chip can
consumption of the ramp-signal buffer is 1.13 mA. In the be obtained. Since the ramp signal of the outermost
case of the 960-channel column driver IC using the channel arrives last, using the absolute-value error at the
RDAC structure, the current consumption of the global time, the output voltage amplitude deviation (AVO:
reference voltage circuit is approximately 4 mA. In the output voltage amplitude deviation) can be also obtained.
proposed column driving technique, taking into account The DVO and AVO of the channels with respect to the
all RGB ramp-signal buffers, the total current operation condition and ramp signal delay are
consumption is approximately 3.39 mA, which is smaller summarized in Table 4. Even under the worst condition,
than the conventional RDAC- based column driver IC. the simulated DVO and AVO are both less than 2 mV,
The simulated waveforms of the ramp signal are where a target spec is under 8 mV.
shown in Fig. 9. The settling time of the ramp signal at
the outermost channel (Vr, f), CH1, is approximately 37.9 3. Sampling Error Reduction for the Ramp Signal-
ns under the slowest operation condition. based Column Driving Circuit
Meanwhile, QCK supplied from the chip center has an
RC delay similar to that of the ramp signal. The holding In analog voltage sampling circuits, to minimize errors
signal (QS) is generated fastest for CH478 located at the caused by environmental noise, differential-ended signals
chip center and slowest for CH1, the outermost channel. are mainly used. However, in the AMOLED column
From a result of the delay difference of the two extreme driver IC, which should process analog outputs withJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.4, AUGUST, 2019 353
Fig. 10. Proposed sampling circuit used to reduce sampling
errors.
gamma characteristics, it is not appropriate to use
differential-ended signals. Therefore, in this work, a
sampling circuit using single-ended signals, which have a Fig. 11. 20-Channel Layout of the Proposed Column Driver IC.
small area and simple circuit design, is applied. At this
time, the possible errors, which may occur in the ramp input of the output amplifier and the ramp signal (Vr)
signal sampling circuit, are minimized using the analog have different settling behaviors from each other. Thus,
circuit design techniques as shown in Fig. 10. even after VSX is held at the (+) node of the amplifier, Vo
If the sampling switch is implemented using a MOS which is connected to the (-) node continues moving
transistor, channel charges can be injected into the source towards the target voltage. At this time, output kickback
and drain nodes when the MOS transistor turns off. The may occur, causing Vo to move the sampled input with
injected channel charge, QCH, expressed as Formulas (2) VSX [11]. In this paper, errors caused by output kickback
and (3) may degrade the image quality of the AMOLED are minimized by using the source follower as the input
panel. In (2) and (3), VGS is determined as a voltage stage of the output amplifier [16].
difference between the sampling signals, QS, and the
input voltage, Vr. To minimize sampling errors caused by IV. PROTOTYPE MEASUREMENT RESULTS
channel charge injection, a differential-ended signal
sampling circuit using the ‘early clock’ and ‘bottom-plate The 96-channel prototype IC, in which the proposed
sampling’ is commonly used. However, in the case of the ramp signal-based column driving technique is applied,
column driver IC, a single-ended signal is used, so it is is implemented using a 0.18 μm CMOS process. The 20-
not easy to apply these circuit design techniques. channel layout is shown in Fig. 11. The effective area per
Furthermore, clock feedthrough generated by the unit channel is 4200 μm2 and when the analog supply
sampling signal and the parasitic capacitance of the voltage and digital supply voltage are 3.3 V and 1.8 V,
sampling switch may degrade DVO and AVO respectively, the static current consumption per unit
performances. Therefore, in this paper, the CMOS channel is 3.0 μA.
sampling switch and the dummy switches are used The measured output waveforms of a single channel
simultaneously to minimize channel charge injection and with respect to display pattern are shown Fig. 12. The
sampling errors caused by clock feedthrough in the rail- measured H-stripe pattern waveform is shown in Fig.
to-rail signal range. 12(a) where the output of the unit channel changes
rapidly at every 1-H period, while the output amplifier
QCH = W × L × COX × (VGS - VTH ) (2) demonstrates the required settling performance of 3.5 μs
W × L × COX × (VGS - VTH ) at worst. The measured H-bar pattern waveform is shown
DVsx = (3)
2CS in Fig. 12(b) where the output of the channel varies by 1
LSB during a single 1-H period, while the gamma output
The output (Vo) connected to the differential-ended characteristics maintain monotonicity.354 TAI-JI AN et al : AREA-EFFICIENT RAMP SIGNAL-BASED COLUMN DRIVING TECHNIQUE FOR AMOLED PANELS
Table 5. Performance Comparison with the Previously Reported Column Driver IC’s
[3] TCASI2010 [5] JSSC2012 [8] JSSC2014 [10] JSSC2013 [16] TCASI2018 This work
Resolution [bits] 8 10 10 9 8 8
6b RDAC + 4b 7b RDAC + 3b 6b RDAC + 3b Amp. 6b RDAC + 2b Amp. 6b Ramp + 2b Amp.
DAC Type 8b RDAC
RDAC CDAC DAC DAC DAC
Analog Supply [V] 5.0 5.0 5.0 5.0 8.0 3.3
Output Range [V] 4.5 4.5 4.5 4.5 5.0 2.4
Max. DVO [mV] 13.2 22.0 5.6 15.9 8.0 6.0
Area/1column 40,960 13,860 5,010 7,800 5,520 4,200
[μm2] (1280ⅹ32) (495ⅹ28) * (334ⅹ15) (390ⅹ20) * (460ⅹ12) (350ⅹ12)
0.35 μm 0.11 μm 0.35 μm 0.13 μm 0.18 μm
Process [CMOS] 0.35 μm
2 Poly 4 Metal 1 Poly 6 Metal 2 Poly 4 Metal 1 Poly 4 Metal 1 Poly 6 Metal
* The area of the holding latch and level shifters is not included.
Fig. 13. Measured DVO Performance of the 96-Channel
Prototype IC.
(a)
The 96-channel prototype IC and the previously
presented column driver IC are compared in Table 5. In
the proposed ramp signal-based column driver IC, the
effective area of the unit channel is 4200 μm2 using the
RGB independent ramp signals and 8-bit resolution,
which is comparable to the results of other studies. The
uniformity based on the DVO is also superior to that of
other studies. This indicates that the proposed ramp
signal-based column driving technique can effectively
minimize the driver IC area while maintaining
performance quality.
(b)
V. CONCLUSIONS
Fig. 12. Measured Channel Output Waveform (a) H-Striped,
(b) H-Bar Patterns.
This work proposes an area-efficient ramp signal-
The output voltage deviations of the 96-channels are based column driving technique for high-resolution
shown in Fig. 13, where the same digital inputs are AMOLED panels. The proposed column driving
applied to all channels the 96-channel prototype IC. The technique achieves column driver IC area reduction of
measured DVO is within ±6 mV less than a target spec, 44.3% by replacing the conventional RDAC-based
and from the fact that no particular pattern is found from column driver IC with a single ramp signal line, while
the chip center to the outermost channel, it is verified that sharing the single ramp signal to vary consecutively in
the RC delay of the ramp signal is minimized at the time among all channels. In addition, each unit channel
required accuracy. of the proposed column driver IC employs a weightedJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.19, NO.4, AUGUST, 2019 355
two-step interpolation topology, composed of the first- Based Capacitor-String Interpolation for Mobile
stage 6-bit ramp signal and the second-stage 2-bit Active-Matrix LCDs," Solid-State Circuits, IEEE
amplifier DAC, to minimize operation speed, area, and Journal of, Vol. 49, No. 3, pp.766-782, March.,
power consumption. 2014.
[9] Y. J. Jeon et al., "A Piecewise Linear 10 Bit DAC
ACKNOWLEDGMENTS Architecture With Drain Current Modulation for
Compact LCD Driver ICs," Solid-State Circuits,
This work was supported by Samsung Display, the IEEE Journal of, Vol. 44, No. 12, pp. 3659-3675,
IDEC of KAIST, the Ministry of Trade, Industry & Dec., 2009.
Energy and Korea Semiconductor Research Consortium [10] C. Lu et al., "A 10-b Two-Stage DAC with an
program for the development of future semiconductor Area-Efficient Multiple-Output Voltage Selector
devices (#10080488), and the MSIT under the ITRC and a Linearity-Enhanced DAC-Embedded Op-
program (IITP-2019-2018-0-01421). Amp for LCD Column Driver ICs," Solid-State
Circuits, IEEE Journal of, Vol. 48, No. 6, pp.
1475-1486, June., 2013.
REFERENCES
[11] C. Lu et al., "A Column Driver Architecture With
Double Time-Division Multiplexing RDACs for
[1] K. Yoneda et al., "Development trends of LTPS
TFT-LCD Applications," Solid-State Circuits,
TFT LCDs for mobile applications," 2001
IEEE Journal of, Vol. 49, No. 10, pp. 2352-2364,
Symposium on VLSI Circuits. Digest of Technical
Oct., 2014.
Papers, 14-16, pp. 85-90, June., 2001.
[12] H. G. Li et al., "High-Precision Mixed Modulation
[2] K. M. Kim et al., “One-Chip Driver IC for 16
DAC for an 8-Bit AMOLED Driver IC," Display
Million Color WXGA LTPS TFT LCD Panel,” SID
Technology, IEEE Journal of, Vol. 11, No. 5, pp.
Symposium Dig. Tech. Papers, May., 2008.
423-429, May., 2015.
[3] C. Lu et al., "An Area-Efficient Fully R-DAC-
[13] J. S. Kang et al., "10-bit Driver IC Using 3-bit
Based TFT-LCD Column Driver," Circuits and
DAC Embedded Operational Amplifier for Spatial
Systems I: Regular Papers, IEEE Transactions on,
Optical Modulators (SOMs)," Solid-State Circuits,
Vol. 57, No. 10, pp. 2588-2601, Oct., 2010.
IEEE Journal of , Vol. 42, No. 12, pp. 2913-2922,
[4] H.-U. Post and K. Schoppe, "A 14-bit monotonic
Dec., 2007.
NMOS D/A converter," Solid-State Circuits, IEEE
[14] R. Hogervorst et al., "A compact power-efficient 3
Journal of , Vol. 18, No. 3, pp. 297-301, June.,
V CMOS rail-to-rail input/output operational
1983.
amplifier for VLSI cell libraries," Solid-State
[5] C. Lu, et al., "A 10-bit Resistor-Floating-Resistor-
Circuits, IEEE Journal of , Vol. 29, No. 12, pp.
String DAC (RFR-DAC) for High Color-Depth
1505-1513, Dec., 1994.
LCD Driver ICs," Solid-State Circuits, IEEE
[15] Y. J. Kim et al., "A 12 bit 50 MS/s CMOS Nyquist
Journal of, Vol. 47, No. 10, pp. 2454-2466, Oct.,
A/D Converter With a Fully Differential Class-AB
2012.
Switched Op-Amp," Solid-State Circuits, IEEE
[6] Y. C. Sung et al., “10bit Source Driver with
Journal of, Vol. 45, No. 3, pp. 620-628, March.,
Resistor- Resistor-String Digital to Analog
2010.
Converter,” SID Symp. Dig. Tech. Papers, April.,
[16] T. J. An et al., "Area-Efficient Time-Shared
2006.
Digital-to-Analog Converter With Dual Sampling
[7] K. Umeda et al., “A novel linear digital-to-analog
for AMOLED Column Driver IC’s," Circuits and
converter using capacitor coupled adder for LCD
Systems I: Regular Papers, IEEE Transactions on,
driver ICs,” SID Symp. Dig. Tech. Papers, May.,
Vol. 65, No. 10, pp. 3227-3240, Oct., 2018.
2008.
[17] Y. S. Park et al., "An 8b Source Driver for 2.0 inch
[8] H. S. Kim et al., "A 10-Bit Column-Driver IC With
Full-Color Active-Matrix OLEDs Made with LTPS
Parasitic-Insensitive Iterative Charge-Sharing
TFTs," 2007 IEEE International Solid-State356 TAI-JI AN et al : AREA-EFFICIENT RAMP SIGNAL-BASED COLUMN DRIVING TECHNIQUE FOR AMOLED PANELS
Circuits Conference. Digest of Technical Papers, Jun-Sang Park received the B.S.
11-15, pp. 130-592, Feb., 2007. and M.S. degrees in electronic
engineering from Sogang University,
Seoul, Korea, in 2012 and 2014,
respectively, where he is currently
Tai-Ji An received the B.S. degree
pursuing the Ph.D. degree. He is a
in electronic engineering from recipient of a scholarship sponsored
University of Seoul, Korea, in 2007, by Samsung electronics. His current interests are in the
and the M.S. and Ph.D. degrees in design of high-resolution low-power CMOS data
electronic engineering from Sogang converters, PMICs, and very high-speed mixed-mode
University, Korea, in 2013 and 2019, integrated systems.
respectively. From 2007 to 2011, he
was with Luxen Technologies, where he had developed Gil-Cho Ahn received the B.S. and
M.S. degrees in electronic engi-
various power-management and analog integrated
neering from Sogang University,
circuits. Dr. An has been with the Samsung Electronics
Seoul, Korea, in 1994 and 1996,
Co., Ltd. and has developed power monitoring IP’s for respectively, and the Ph.D. degree in
low-power mobile application processors. electrical engineering from Oregon
State University, Corvallis, in 2005.
From 1996 to 2001, he was a Design Engineer at
Moon-Sang Hwang received the Samsung Electronics, Kiheung, Korea, working on
mixed analog-digital integrated circuits. From 2005 to
B.S., M.S. and Ph.D degrees in
2008, he was with Broadcom Corporation, Irvine, CA,
electrical engineering from Seoul
working on AFE for digital TV. Currently, he is a
National University, Korea, in 2000, Professor in the Department of Electronic Engineering,
2003 and 2009, respectively. Since Sogang University. His research interests include high-
2009, Dr. Hwang has been with the speed, high-resolution data converters and low-voltage,
Samsung Display Co., Ltd. and has low-power mixed-signal circuits design.
developed display driver IC’s and high-speed interface
for display driver IC and timing controller. His current Seung-Hoon Lee received the B.S.
research interests include design and developing of low- and M.S. degrees in electronic
engineering from Seoul National
power and area efficient display driver IC architecture,
University, Korea, in 1984 and 1986,
high-speed interface for display driver IC, small-size data respectively, and the Ph.D. degree in
converters, sensors and mixed-mode integrated system. electrical and computer engineering
from the University of Illinois,
Urbana-Champaign, in 1991. He was with Analog
Won-Jun Choe was born in Busan, Devices Semiconductor, Wilmington, MA, from 1990 to
1969. 2. 9. He've got Ph.D., M.S. and 1993, as a Senior Design Engineer. Since 1993, he has
been with the Department of Electronic Engineering,
B.S. degrees from E.E. of Seoul
Sogang University, Seoul, where he is currently a
National University, E.E. of Seoul
Professor. His current research interests include design
National University, and E.E. of and testing of high-resolution high-speed CMOS data
Pusan National University respec- converters, CMOS communication circuits, integrated
tively. He has worked for Samsung sensors, and mixed-mode integrated systems. Dr. Lee has
Display since 2012, and he has 25 years experience on been a member of the editorial board and the technical
display electronics. His major is about circuitary for program committee of many international and domestic
journals and conferences including the IEEK Journal of
display driving, and display interface technologies.
Semiconductor Devices, Circuits, and Systems, the IEICE
Recently, he has researched OLED driving technology,
Transactions on Electronics, and the IEEE Symposium
especially about uniformity, life time, and high BW on VLSI Circuits.
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