5TH IEEE INTERNATIONAL TEST CONFERENCE INDIA (ITC INDIA) 2021 - Proceedings 18-20, July 2021
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5TH IEEE
INTERNATIONAL TEST CONFERENCE INDIA
(ITC INDIA) 2021
Proceedings
18-20, July 2021
https://itctestweekindia.org
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5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
CONTENTS
Contents Page No.
Message from ITC India 2021 Team 2
Committee 4
Program Schedule 5
Tutorials 12
Keynotes 18
Panel Discussion 24
Technical Sessions 27
Sponsors 45
1
5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Message from ITC India 2021 Team
Greetings!
We welcome you to 5th IEEE International Test Conference India (ITC India 2021). One of the primary
goals of ITC India is to serve the professional and academic communities mainly of Indian subcontinent by
presenting the highest quality technical program. At ITC India, design, test and yield professionals can
confront challenges faced by the industry and learn how these challenges are being addressed by the
combined efforts of academia, EDA tool and equipment suppliers, designers, and test engineers.
Like every year, we have come up with a rich technical conference program with 5 keynotes from
distinguished speakers in the industry, 6 tutorials. There are also sessions from ART and TRC tracks,
special session, invitee talks and a panel discussion.
Tutorials program in ITC India gives a great opportunity to aspiring DFT/Test Engineers, students and
experienced DFT professionals to learn, relearn, upskill or revise DFT/Test skills from the very best in our
Industry.
ITC India 2021 has been bringing to you every year tutorial session with the intention to share knowledge
across the industry and academics. Every year ITC India has included various aspects and topics of VLSI
Testing as a part of the program. We have seen speakers, presenters and participants from various parts of
the world and virtual mode of presentation has made possible interaction among these people. This year,
yet again, with the same intention we are bringing to you Tutorial Program from various EDA houses,
Universities and Product companies. ITC India has lined up speakers with years of experience, from
Industry and academia, across the world. Participants from various time zones will be interacting with
these speakers in ITC India 2021. Let us all utilize this opportunity and meet virtually on 18th July 2021
with the aim to learn on this day.
TRC track is a great platform for DFX/Test professionals to publish their ongoing work, share their
valuable opinions and get a pulse from their peers and experts on solutions to long standing or new
DFX/Test challenges.
Academia Research Track will give the students and young academicians a great platform to share their
creative research ideas, getting feedback on an innovative method, or participating without having to write
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5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
a full paper. The high-quality posters/short papers will be published in IEEE Explore along with ITC main
conference proceedings.
ITC India has been offering generous fellowships to students and teachers of various Indian academic
institutions. The fellowship provides complimentary registration to attend all the Tutorials, Keynotes and
Technical Sessions. This year 186 fellowships are awarded to the Faculty members, Research scholars and
UG/PG students from Indian academic institutions across India to attend ITC India.
We are indebted to all the financial sponsors Qualcomm, Intel, Synopsys, Cadence, Siemens and Tessolve
Semiconductors for their generous contribution to ITC India 2020. We express our gratitude to IEEE
Bangalore section for supporting this event with financial co-sponsorship. As with last year, the ITC India
2021 proceedings will be available online through IEEE Explore and other scientific databases.
We thank the members of ITC India committee, Reviewers, TTTTC Volunteers, IESA and VLSI Society
of India for their diligence and dedication towards making this event a success.
Let us plan to partake this banquet of knowledge, virtually and continue to march forward as a well-
connected test community.
We look forward to an enthusiastic participation from all of you!
ITC India 2021 Team
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5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Committee
General Chair
Navin Bishnoi, Marvell India Pvt. Ltd.
Technical Program Co-Chairs
Srinivas Vooka, Google
Sameer Chillarige, Cadence
Venkata Rangam Totakura, Infineon
Tutorials Co-Chairs
Shamitha Rao, Intel India
Anurag Jain, Broadcom Inc
Test Reality Check Co-Chairs
Kamlesh Pandey, Qualcomm
Kavitha Shankar, Marvell Semiconductors India
Academia Track Co-Chairs
Philemon Daniel, NIT Hamirpur
Ankush Srivastava, Qualcomm India Pvt Ltd
Prof. Virendra Singh, IIT Bombay
Subhadip Kundu, Qualcomm India Pvt Ltd
Communication/Website Co-Chairs
Kavitha Shankar, Marvell Semiconductors India
Anurag Jain, Broadcom Inc
IEEE Liaison
Dr. Sivanantham S, VIT, Vellore
Prakash Narayanan, Texas Instruments
Fellowship And Publication Co-Chairs
Dr. Sivanantham S, VIT, Vellore
Dr. Sree Ranjani Rajendran, FICS Research Lab, University of Florida, Gainesville.
Branding/Marketing Chair
Veeresh Shetty, Mentor – A Siemens Business
Registration
Neelakandan Eswaran, Altran Technologies
Finance
Krishnan Sreenivasan, AB Innovative
V. Veerappan, TESSOLVE
4
5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Program
Schedule
5
5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Program Schedule
Tutorials:
Sunday, July 18, 2021
8:30 am – REGISTRATIONS
9:30 am
TRACKS TRACK 1 TRACK 2 TRACK 3
Session Chair: Anurag Jain Session Chair: Shamitha Rao Session Chair: Kavitha Shankar
HALL
NAME
Zoom Meeting Zoom Meeting Zoom Meeting
9:30 am – T1 : Identifying Good, Bad and T2 : Advanced DFT and Security T3 : Addressing Test, Safety and Security
11:00 am Ugly chips through DFT : A Technology for AI chips for Connected Automotive IC’s
(15 mins. Primer on VLSI Testing
Break) Lee Harrison, Peter Orlando, Gajinder Panesar, Nilanjan Mukherjee,
11:15 am – Abhishek Chaudhary Jay jahangiri Raghav Mehta, Lee Harrison
12:45 pm (Texas Instruments India) (Siemens EDA) (Siemens EDA)
Nir Sever, Gal Carmel (protean Tecs)
12:45 pm – LUNCH BREAK
1:45 pm
1:45 pm – T4 : Testing Power and Clock T5 : Device-Aware-Test for T6 : New Directions in Semiconductor Test
3:15 pm Networks Emerging Memories: The means to and Validation
(15 mins. win the war against unmodeled
Break) Prof. Shi-Yu Huang (Professor, faults Dr. C P Ravikumar (Texas Instruments
3:30 pm – Faculty of Electrical Engineering India)
5:00 pm Department, National Tsing Hua Said Hamdioui (Delft Universitty of
University, Taiwan) Technology)
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5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Conference:
Monday, July 19, 2021
8:00am-
REGISTRATIONS
9:00am
SESSIONS Morning Keynotes
Meeting Links
Zoom Meeting
9:00am –
Inauguration/Welcome | Navin Bishnoi, General Chair, ITC India 2021
9:10am
9:10am – Keynote 1: “The Critical Role of Analytics from Silicon to Systems” | Amit Sanghani,
9:50am Sr. Vice President – Hardware Analytics and Test, Synopsys
9:50am – Keynote 2: “Test Optimization for High-Performance, Advanced Technology SOCs” | Phil Nigh,
10:30am Distinguished Technical Staff Member, ASIC Product Division, Broadcom
10:30am –
TEA/COFFEE BREAK SESSION
11:00am
Session 1 – High Quality Memory Test & Advanced Session 2 – Functional Safety & Hardware
SESSIONS Fault models Security
Session Chair: Venkata Rangam Totakura Session Chair : Prof Indranil Sen Gupta
HALL NAME
Zoom Meeting Zoom Meeting
1.1 Addressing High Speed Memory Interface Test 2.1 Parallel Field Test Architecture for Boot-
Quality Gaps in Shared Bus Architecture ROMs in Safety-Critical SoCs
Wilson Pradeep, Rajesh Gottumukkala and Srinivas Nitesh Mishra, Nikita Naresh and Aravinda
Vooka Acharya
1.2 Core Test Language based High Quality 2.2 Comprehensive In-field Memory Self-Test and
Memory Testing and Repair Methodology ECC Self Checker –Minimal Hardware Solution
for FuSa
11:00am- Puneet Arora, Patrick Gallagher and Steven Gregor
12:30pm 1.3 Targeting Zero DPPM through Adoption of Ratheesh Thekke Veetil, Ramesh Sharma and
Advanced Fault Models and Unique Silicon Fall-out Swapna Gundeboyina
Analysis
2.3 Side-channel Analysis for Hardware Trojan
Aravinda Acharya, Nikita Naresh, Prakash Detection using Machine Learning.
Narayanan, Rubin Parekhji, Wilson Pradeep, Kevin
Roush, Humberto Ibarra, Raj Sheth and Clarence Shuo Yang, Prabuddha Chakraborty and Swarup
Flora Bhunia
12:30pm-
LUNCH BREAK
1:30pm
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5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Monday, July 19, 2021
Test Reality Check (TRC) Track Academia Research Track (ART)
SESSIONS
Session Chair | Kavitha Shankar Session Chair | Ankush Srivastava
HALL NAME
Zoom Meeting Zoom Meeting
TRC1.1 In Silicon Soft Error Injection DFT ART 1.1 Adapting AI into Low Power Testing
Technique for RAM REPAIR validation
Hillol Maity, Santanu Chattopadhyay
Avinash Rath, Sanjith Sleeba, Atul Sonwani
TRC1.2 Yield Improvement techniques in Slow- ART 1.2 Logic Locking: The Future of Secure
Slow Devices during High Volume Manufacturing Hardware Design (Invited)
Ananthashayana M S Rajit Karmakar
1:30pm- TRC1.3 ScanDump made Easy! – An IJTAG based ART 1.3 Understanding Test Escapes from
3:00pm approach Classical Stuck-at and TDF Tests (invited)
Nagendra Kommuri, Srijesh Parambath Prof Adit D. Singh, Auburn University US
TRC 1.4 Innovative ways to address FPGA
prototyping challenges of DFT IP
Mohammed Akhil P R, Ravi Ramachandran,
Praneeth Kumar R, Milind Sonawane, Sailendra
Chadalavada and Sanjith Sleeba
3:00pm-
TEA/COFFEE BREAK SESSION
3:30pm
Poster Session 1 Poster Session 2
SESSIONS Session Chair | Kavitha Shankar and Vineet Session Chair | Kamlesh Pandey and Amanullah
Srivastava Khan
HALL NAME
Zoom Meeting Zoom Meeting
Poster 1.1 Left Shift & Correct by Construction Poster 2.1 Automating silicon ATE bringup
DFT-RTL Design
Avinash Rath, Sanjith Sleeba, Krishna Rajan, Jae
Sudhakaran Nikhil, Gauri Shankar Singh, Gaurav Wu and Amit Sanghani
Vashisht, Bhaskar Kaushik and Mohammed Zuber P
Malek Poster 2.2 Novel Approach for DFT Test time
Reduction
3:30pm- Poster 1.3 DFT Strategy for Safety devices with
4:30pm Ashutosh Anand, Shreyans Rungta, Souvik Sarkar,
Aging Detection Requirements
Surya Pratap Singh, Abhishek Bhattacharya,
V Srinivasan, Manish Sharma, Shivkumar Vats and Piyush Kumar Chaurasia, Srinivasa Rao Dasari
Tripti Gupta and Mona Shah
Poster 2.3 Effective defect screening techniques:
Poster 1.4 Memory interface faults and the PPM The outright need of high-quality test
requirements – The indecisive ram-sequential test
Vineeta Shukla, Karthik Reddy, Hardik Bhagat and
Karthik Reddy Balaji Upputuri
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5th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Monday, July 19, 2021
Poster 1.5 Spyglass Netlist level Check – Poster 2.4 A Novel Approach to minimize
Methodology on Low Power Mixed Signal Design Coverage Drop between Pre-PnR to Post-PnR
Netlist in SoC VLSI Design
Sriram Prasath Sekar, Sreenivasa Rao Vuttaravilli
and Shivam Sharma Anil Ingale, Chandan Gupta, Satish Chandra and
Jatin Balsaraf
Poster 1.6 A Survey of Embedded Memory Testing
Poster 2.5 Configurable Scan Wrapper
Karthika S, Shenbagavalli A Architecture
Hanumantharaya H, Ratheesh T Veetil and Anvesh
Gadi
Poster 2.6 High throughput Multiple Device
Diagnostics for Hierarchical Test Designs
Sameer Chillarige, Bharath Nandakumar and Atul
Chhabra
HALL NAME
Zoom Meeting
Invited 1: Design Closure and Test Challenges in Addressing Automotive Quality with High-speed IO
4:30pm- Interfaces
5:00pm Lei Wu, Rajagopal K.A, Devanathan Varadarajan
Texas Instruments
5:00pm-
Day 1 – Closing / Wrap-up
5:05pm
Tuesday, July 20, 2021
8:00am-
REGISTRATIONS
9:00am
Meeting Link
Zoom Meeting
9:00am-
Welcome | Navin Bishnoi, General Chair, ITC India 2021
9:10am
9:10am- Keynote 3: “Tackling the test challenges of the chiplet revolution”
9:50am Jeff Rearick, Senior Fellow, Advanced Micro Devices
9:50am – Keynote 4: “Elevating 2D Design and Test to 3D” | Vivek Chickermane,
10:30am Distinguished Engineer, Cadence
10:30am –
TEA/COFFEE BREAK SESSION
11:00am
95th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Monday, July 19, 2021
Invited Talk & Panel Discussion
SESSIONS
Session Chair | Kamlesh Pandey
Meeting Link
Zoom Meeting
11:00am- Invited 2: “IEEE P2851 Standards on Functional Safety Interoperability”
11:30am Jyotika Athavale, NVIDIA
Panel Topic: Has the era of packetized scan architecture arrived?
11:30am- Panelist: Punit Kishore (Qualcomm, Bangalore), Geir Eide (Siemens EDA, USA), Akshaye Sama
12:30pm (Broadcom, UK), Animesh Khare (Nvidia, Bangalore), Denis Martin (Synopsys, USA)
Moderator: Kamlesh Pandey (Qualcomm, Bangalore)
12:30pm-
LUNCH BREAK
1:30pm
Session 3 – Best Practices in Accelerated Pre-Silicon Session 4 – Power Aware Test Prediction &
SESSIONS Verification, Analog & Stress Testing Optimization
Session Chair: Prof Dr. Jaya Gowri Session Chair : Srinivasan Chandrasekaran
Meeting Link
Zoom Meeting Zoom Meeting
3.1 Accelerating GLS Simulation closure in DFT 4.1 A Fast Robust Operation Mode invariant
with Emulator Hardware Frame-work for IR drop Prediction
Kriti Das, Padmini Prakash and Abhimanyu Zala Utsav Jana, Gaurav Jain, Nachiket Soman, Vineeth
Kaimal, Ankita Agarwal and Deepak Agarwal
3.2 Method and Apparatus for Bug Free Rapid
4.2 An Improved Test Pattern Reordering
Silicon Bringup
Framework Targeting Test Power Reduction
Ravikumar Patel, V N Sivakumar Avvaru, Ashutosh Hillol Maity, Santanu Chattopadhyay, Indranil
Anand, Kirankumar Tatti, Prakash Kumar and Sengupta, Girish Patankar and Parthajit
Shokhi Rastogi Bhattacharya
1:30pm- 3.3 A Novel Method to measure PLL Bandwidth in 4.3 16x Multisite, High Current and High Power
3:30pm a 5G RF transceiver density Test Solution for Power Protection Device
Pradeep Nair and Dineej A Sangeetha M V and Gaurav Mittal
3.4 An Efficient Test Architecture for Concurrent 4.4 Runtime Test Solution for Adaptive Power
Over Voltage Stress Testing (OVST) of Logic and Optimization of Edge AI devices
Memory
Vincent Huard, Olivier Montfort, Souhir Mhira,
Snehil Agrawal, Kamlesh Pandey, Ravi Chandra Mathieu Louvat, Francois Jacquet, Lorenzo Zaia,
Kumar Y and Anurag Jain Francois Bertrand, Eddy Acacia, Olivier Caffin,
Hela Belhadj, Olivier Durand, Nils Exibard,
Vincent Bonnet, Alexandre Charvier, Paolo
Bernardi and Riccardo Cantoro
105th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Monday, July 19, 2021
3:30pm-
TEA/COFFEE BREAK SESSION
4:00pm
Closing Ceremony
SESSIONS
Session Chair | Navin Bishnoi
Meeting Link
Zoom Meeting
Keynote 5: “Design-for-Testability: Setting the Cornerstone for Successful Manufacturing” | John
4:00pm- Carulli,
4:30pm
Director, PostFab Test Development Center, GLOBALFOUNDRIES
4:30pm-
Conference Closing/Wrap-up
4:40pm
115th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Tutorials
125th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Tutorial 1
Title: "Identifying Good , Bad and Ugly Chips Through DFT: A
Primer on VLSI Testing"
Abhishek Chaudhary
Bio:
Abhishek Chaudhary is an experienced DFT Engineer with 14 years of experience in the
semiconductor industry. He is presently working at Texas Instruments Bangalore. Prior to
joining TI, he led the team of engineers that owned DFT for all IPs, testchips and
bufferchip ASIC designs developed worldwide at Rambus. Prior to Rambus, Abhishek
worked at Freescale Semiconductor where he worked primarily on DFT for automotive
chips.
Abhishek has a passion for continued education and has been an active participant in IEEE TTTC events and has
presented on DFT topics at various external events and conferences. Abhishek holds a Master’s degree from IIT
Delhi and Bachelors from Visvesvaraya National Institute of Technology, Nagpur.
Tutorial 2:
Title: "Advanced DFT and Security Technologies for AI Chips"
Jay Jahangiri
Bio:
Jay Jahangiri is a Product Manager for Tessent products at Siemens EDA (Siemens Digital
Industry Software). He has over 25 years of experience in various DFT disciplines including
ATPG, compression, BIST, and boundary scan. Jay worked as a DFT engineer for Texas
Instruments and Raytheon prior to joining Siemens EDA. He is the co-inventor of two US
patents related to silicon test and holds a Bachelor of Science degree in Electrical Engineering
and an MBA. Jay has published numerous papers and articles in the area of silicon test.
Lee Harrison
Bio:
Lee Harrison is Automotive IC Test Solutions Manager, at Siemens EDA. He has
over 20 years of industry experience with Tessent DFT products and has been involved in the
specification of new test features and methodologies for Siemens customers, delivering high
quality DFT solutions. With a focus on automotive, Lee is working to ensure that current and
future DFT requirements of Siemens’s automotive customers are understood and met. Lee
received his BEng in MicroElectronic Engineering from Brunel University London in 1996.
135th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Peter Orlando
Bio:
Peter has been working for Siemens in Wilsonville, Oregon since June 2018 as a member of
Tessent DFT products division. During his time at Siemens, he has been focusing on the
development and deployment of the Streaming Scan Network (SSN) product. Prior to joining
Mentor, Peter has worked in the silicon industry for 25 years for such companies as Marvell
Semiconductor, Micron Technology, ST Microelectronics, and LSI logic.
Tutorial 3:
Title: "Addressing Test, Safety And Security for Connected
Automotive ICs"
Gajinder Panesar
Bio:
Gajinder Panesar is a Fellow at Mentor, A Siemens Business. One of Europe’s leading SoC
architects, Gadge’s experience includes senior architecture definition and design roles within
both blue-chip and start-up environments. He holds more than 50 patents and is the author of
more than 20 published works. Gajinder was CTO at UltraSoC prior to the company’s
acquisition by Mentor-Siemens. He has also held roles at NVIDIA (NASDAQ:NVDA); and
Picochip, where he was Chief Architect, a role in which he continued after the company’s
acquisition by Mindspeed Inc (NASDAQ:MSPD). His previous experience includes roles at
STMicroelectronics, INMOS, and Acorn Computers. He is a former Research Fellow at the
UK’s Southampton University, and a former Visiting Fellow at the University of Amsterdam.
Nilanjan Mukherjee
Bio:
Nilanjan Mukherjee is a Senior Engineering Director for Tessent Silicon Lifecycle
Solution Division at Siemens Digital Industries Software (DISW). He has been with
Siemens (previously Mentor) for almost two decades, where he is involved in the
research and development of key technologies in the areas of test compression, Logic
BIST, Memory BIST, low power DFT, and memory test/diagnosis. Some of his major
accomplishments include being a co-inventor and an architect of the Embedded
Deterministic Test (EDT) technology, the VersaPoint Test Points technology, a Low
Power Hybrid EDT/Logic BIST scheme for automotive ICs, and the Observation Scan
Technology for Logic BIST. Currently, his focus is on developing new solutions and
methodologies for improving the quality and reliability of automotive ICs. Prior to
joining Mentor Graphics, he worked at Lucent Bell Laboratories in New Jersey.
As a researcher, Nilanjan has co-authored more than 85 technical papers for various conference proceedings and
archival journals. He is a co-inventor of 52 US patents and several international patents. He has received numerous
awards and recognition including the Best Paper Award at VTS 2020, Siemens Digital Industries Software Invention
of the year 2019, the Most Significant Paper Award at ITC 2012, the Best Paper Award at VLSI Design in 2009, the
Donald O. Pederson Outstanding Paper Award from the IEEE Circuits and Systems Society in 2006, the Teruhiko
Yamada Memorial Best Student Paper Award at ATS 2001, and the Best Paper Award at VTS 1995. Nilanjan
received a B.Tech. (Hons) degree from IIT, India, and a Ph.D. degree from McGill University, Canada. He has given
numerous tutorials and invited talks at DAC, ITC, VTS, ATS, and VLSI Design, and has offered many short term
courses on DFT.
145th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Raghav Mehta
Bio:
Raghav Mehta is Technology Enablement Engineer at Siemens. He specializes in automotive
DFT implementation. Over last couple of years, he has focused on consulting efficient flow
methodology for automotive ICs. At Siemens, Raghav has co-created custom MBIST
solution for various different memories. His work focuses on memory testing, built in test
technologies for logic and memory and DFT for automotive. Raghav achieved his MS degree
in VLSI system design from University of Southern California, United States
Lee Harrison
Bio:
Lee Harrison is Automotive IC Test Solutions Manager, at Siemens EDA. He has over 20
years of industry experience with Tessent DFT products and has been involved in the
specification of new test features and methodologies for Siemens customers, delivering high
quality DFT solutions. With a focus on automotive, Lee is working to ensure that current
and future DFT requirements of Siemens’s automotive customers are understood and met.
Lee received his BEng in MicroElectronic Engineering from Brunel University London in
1996.
Gal Carmel
Bio:
Gal Carmel, EVP, GM Automotive, proteanTecs. An Automotive and Product entrepreneur
with a proven track record of over 15 years in rapidly honing emerging technologies, markets
and opportunities, both on business and diverse R&D aspects. Before joining proteanTecs, Gal
served as Chief Technology and Production Engineering of Samsung Smart Machines,
building from the ground-up Samsung’s ADAS/AV technology, focusing on full-stack
platforms for automated driving systems. Prior to that, he held key roles in some of the most
innovative pillars of autonomous driving at Mobileye (acquired by Intel), a leading supplier of
Advanced Driver Assist Systems (ADAS). In 2016, Gal brought up Mobileye’s Road
Experience Management (REM) technology for data harvesting and localization engine, enabling full autonomy.
And in 2013, he brought to production its first Mono Vision Camera AEB (Autonomous Emergency Braking),
reaching 5 Star Euro NCAP rating for the most advanced production programs OEMS (Audi, BMW, Nissan). Gal
holds a BSc in Electrical Engineering from Tel Aviv University.
Nir Sever
Bio:
Nir Sever is an industry veteran with over 30 years of technological and managerial
experience in advanced VLSI engineering. Before joining proteanTecs, Nir served for 10
years as the COO of Tehuti Networks, a pioneer in the area of high-speed networking
Semiconductors. Prior to that, he served for 9 years as Senior Director of VLSI Design
and Technologies for Zoran Corporation, a recognized world leader in Semiconductors
for the highly competitive Consumer Electronics market. Nir was responsible for driving
Zoran’s silicon technologies and delivering more than 10 new silicon products each year.
Prior to that, Nir held various managerial and technological VLSI roles at 3dfx
Interactive, GigaPixel Corporation, Cadence Design Systems, ASP Solutions, and Zoran Microelectronics. Nir holds
a B.Sc in Electrical Engineering from The Israel Institute of Technology, Technion.
155th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Tutorial 4:
Title: "Testing Clock and Power Networks"
Shi-Yu Huang
Bio:
Shi-Yu Huang received his Ph.D. degree in Electrical and Computer Engineering from
University of California, Santa Barbara, in 1997. Since 1999, he has joined National Tsing Hua
University, Taiwan until now. He recent research is concentrated on all-digital timing circuit
designs, such as all-digital phase-locked loop (PLL), all-digital delay-locked loop (DLL), time-
to-digital converter (TDC), and their applications to parametric fault testing and reliability
enhancement for 3D-ICs. He has published more than 160 refereed technical papers. Dr. Huang
ever co-founded a company in 2007-2012, TinnoTek Inc., specializing a cell-based PLL
compiler and system-level power estimation tools. He received the best-presentation award or
best-paper awards from several IEEE technical meetings, (i.e., VLSI-DAT’2006, VLSI-DAT’2013, ATS’2014,
WRTLT’2017, ISOCC’2018). He is a senior member of IEEE.
Tutorial 5:
Title: "Device-Aware-Test for Emerging Memories: The Means
to Win the War Against Unmodeled Faults"
Said Hamdioui
Bio:
Hamdioui is currently Chair Professor on Dependable and Emerging Computer
Technologies, Head of the Quantum and Computer Engineering department, and also
serving as Head of the Computer Engineering Laboratory (CE-Lab) of the Delft University
of Technology, the Netherlands. He is also co-founder and CEO of Cognitive-IC, a start-
up focusing on hardware dependability solutions and consultancy.
Hamdioui received the MSEE and PhD degrees (both with honors) from TUDelft.
Prior to joining TUDelft as a professor, Hamdioui spent about seven years within industry
including Intel Corporation (Califorina, USA), Philips Semiconductors R&D (Crolles, France) and Philips/ NXP
Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: emerging technologies and
computing paradigms (including memristors, in-memory-computing, neuromorphic computing, low power HW
architecture for edge AI, etc.), and hardware dependability (including Testability, Reliability, Hardware Security).
Hamdioui owns many patents, has published one book and contributed to other two, and had co-authored over
250 conference and journal papers. He has consulted for many worldwide leading semiconductor companies . He is
strongly involved in the international community as a member of organizing committees or a member of the
technical program committees of the leading conferences. He delivered dozens of keynote speeches, distinguished
lectures, and invited presentations and tutorial at major international forums/conferences/schools and at leading
semiconductor companies. Hamdioui is a Senior member of the IEEE, Served as Associate Editor of IEEE
Transactions on VLSI Systems (TVLSI) [215-2018], Journal, the Journal of Electronic Testing: Theory and
Applications (JETTA) [2011-2019], Elsevier Microelectronic Reliability [2019-2020]; and he serves on the editorial
board of IEEE Design & Test, and ACM Journal on Emerging Technologies in Computing (JETC). He is also
member of AENEAS/ENIAC Scientific Committee Council (AENEAS =Association for European NanoElectronics
Activities). He is also EEE Circuits and Systems Society (CASS)Distinguished Lecturer.
165th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Hamdioui is the recipient of many international/national awards. E.g., he is the recipient of European Design
Automation Association Outstanding Dissertation Award 2001; European Commission Components and Systems
Innovation Award in 2020; the 2015 HiPEAC Technology Transfer Award; and many Best Paper Awards
(DATE’20, ICCD’15, LATS’18, DTIS’15, IVLSI’16, FCST’17); Teacher of the Year Award at the faculty of
Electrical Engineering, Delft University of Technology, the Netherlands, 2017;. In addition, he is a leading member
of Cadence Academic Network on Dependability and Design-for-Testability.
Tutorial 6:
Title: "New Directions in Semiconductor Test and Validation"
Dr. C.P. Ravikumar
Bio:
Dr. C.P. Ravikumar is the Director of Talent Development at Texas
Instruments, India. He is also an adjunct faculty of EE at IIT Madras. Before
joining TI India in 2001, Ravikumar was a Professor of Electrical Engineering
at IIT, Delhi (1991-2001). He also held a visiting position at the University of
Southern California (1995-1996) and the position of Vice President (Training)
at Controlnet India Pvt Ltd (2000-2001). He obtained his Ph.D. (Computer
Engineering) from the University of Southern California (1991), M.E. in
Computer Science with highest scores from Indian Institute of Science (1987)
and B.E. in Electronics with a Gold Medal from Bangalore University (1983).
He has published over 200 papers in leading International conferences and
journals. He has 4 US patents in the area of VLSI Test. He founded the VLSI Design and Test Symposium
(VDAT) and was the General Chair of this event from its inception in 1998 for 15 years. He is the
author/editor/coauthor of over 15 books in areas of VLSI and has contributed several book chapters. He has
served as an associate editor of IEEE Transactions on Circuits and Systems and has served on editorial board
of the Journal of Electronic Testing – Theory and Applications and the Journal of Low Power Electronics.
He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test
Symposium (2005). He founded the Bangalore chapter of IEEE CAS society and was its honorary secretary
for 15 years, and served as the honorary secretary of VSI for 6 years. He has served on the Execom of IEEE
Bangalore Section (2017-2019). He is a Fellow of the INAE and a Senior Member of IEEE.
175th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Keynotes
185th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Title: "The Critical Role Of Analytics From Silicon To Systems"
Amit Sanghani
Speaker Biography:
Sr. Vice President – Hardware Analytics and Test
Head of the Hardware Analytics and Test with end-to-end focus on R&D, Marketing, Solution and
Application
Prior to Synopsys was with Intel PEG as VP-Test for DFT, Automotive and FuSa related central engineering
methodology and Architecture.
At Nvidia was Sr Director of VLSI design and test group for all product ranging from GPU, CPU, SOC etc.
Drove the ISO 26262 Automotive In system test solutions and process and methodology for Nvidia.
Worked at Sun Microsystem on Microprocessor design/test, CAD, VLSI circuits and network Asics.
25+ years of experience in Design, Test, Automation, Software and silicon engineering
Abstract:
The lifecycle management of semiconductor products is changing the way the chip industry
thinks about device performance, health and predictability. At each lifecycle stage, there is a growing opportunity for
meaningful data to be generated and analysed. This deep insight across the design, manufacturing, test and in-field
deployment phases will enable decision making, helping to improve yield, quality and reliability, whilst also
shortening product time to market. Once silicon is deployed into systems in the field, analytics can be conducted on
large sample data sets, across entire product ranges or fleets, providing visibility of longer-term trends to enhance
performance optimization and resilience.
Opportunities gather pace for developing new, insightful sensing and analytics technologies that resonate with
customer and partner ecosystems alike. Silicon Lifecycle Management is one of the most exciting areas of growth for
the semiconductor industry and has emerged as a key area of focus for Synopsys. The nexus of test with lifecycle
management is an exciting area of development and will create significant value and growth for this audience in the
coming years.
195th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Title: "Tackling The Test Challenges Of The Chiplet
Revolution"
Jeff Rearick
Speaker Biography:
Jeff Rearick is a Senior Fellow with Advanced Micro Devices, where he has worked for 15 years and leads
the DFT Strategy team. Prior to joining AMD, Jeff worked at HP/Agilent for 22 years on DFT methodology and
implementation for a variety of microprocessor and networking chips. He served as Editor for the IEEE 1687
standard, currently holds that same role for both the IEEE P1687.1 and P1687.2 Working Groups, and is a member
of the P2427 Working Group; he was a founder of all four of those efforts. He was also a member of the IEEE
1149.6 working group and co-authored the first publication of an implementation of that standard. He has published
dozens of other technical papers and presentations, holds over 40 patents, and is an active member of the Test
Technology Standards Committee as well as the program committees of the International Test Conference and the
European Test Symposium. He earned B.S.E.E and M.S.E.E degrees from Purdue University and the University of
Illinois, respectively, and was the recipient of the Bob Madge Innovation Award in 2016 and the Hans Karlsson
Award from the IEEE Computer Society in 2018.
Abstract:
As we enter the “More than Moore” era of semiconductor integration, chiplets have emerged as a leading
technology vector and show great promise as a platform for many products. As with most new technologies, they
also bring with them many new challenges, including several for the test community. This presentation will give an
overview of the motivation behind and the benefits of chiplet-based architectures, discuss some specific challenges
associated with testing chiplets and chiplet-based systems, and suggest some avenues that the test community can
take to address these issues.
205th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Title: "Design-For-Testability: Setting the Cornerstone for
Successful Manufacturing"
John Carulli
Speaker Biography:
John Carulli is the Director of the PostFab Test Development Center at GLOBALFOUNDRIES. He joined
GF in 2014, based in Malta, NY. He previously had 21 years at Texas Instruments where he was a Distinguished
Member of the Technical Staff. John has held technical and management positions across product lines, technology
development, and operations. His research interests include product reliability, outlier analysis, machine learning,
performance modeling, logic diagnosis, and security.
John holds 8 US Patents. He has over 50 publications in the areas of reliability, test, security, and process
development. He is co-recipient of two Best Paper Awards and two Best Paper Nominations working in close
collaboration with university partners. John serves on the organizing or program committees of several conferences
including the International Test Conference, VLSI Test Symposium, and European Test Symposium. He is a Senior
Member of IEEE. He received his B.S.E.E. and M.S.E.E. degrees from the University of Vermont in Burlington, VT.
Abstract:
Design-for-Testability is the foundation of chip design in every market. From large digital System-on-Chip to
relatively smaller integrated circuits in analog, mixed-signal and RF, a successful end-product requires early
collaborative design consideration. Our manufacturing partners rely on this infrastructure to drive yield, quality,
delivery, and cost. Our end-customers additionally rely on these capabilities to have confidence in product reliability,
safety and security. In this presentation we will discuss some examples of how your “DFT” efforts are leveraged in
the silicon life cycle.
215th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Title: "Test Optimization For High-Performance, Advanced
Technology SOCs"
Phil Nigh
Speaker Biography:
Phil is a Distinguished Technical Staff Member in Broadcom’s ASIC Product Division. He is responsible for
driving quality & test improvements for 7nm, 5nm and 3nm products. He has worked in IC testing for 38 years —
including for IBM & GlobalFoundries — and has over 25 patents. Phil has also organized the “Industry Test
Challenges” workshop for over 20 years — and is on the Program Committee for a number of conferences and
industry groups. Phil has a PhD from Carnegie Mellon University.
Abstract:
Advanced technology products are causing discontinuities in how we Test ICs. The following are some of the
challenges we are facing. I’ll summarize the challenges — and provide some practical solutions to address these
challenges.
The increasing size of ICs are driving changes to production testing — or the IC test costs will
significantly impact product costs.
Quality requirements is challenging our Test capabilities. In addition to ATE testing, will we need to apply
System-level Testing (SLT) to more ICs moving forward?
How should we address both board/system level IC quality — and optimize across both wafer/Final Test &
system-level test steps.
What is the best mix of IC tests moving ahead? How can we enable both high quality & rapid yield/defect
learning with reasonable test cost?
Heterogeneous Integration is enabling faster time to market for leading edge products — but it is also driving
changes to Test approaches & DFT for chiplets & multichip applications.
How can Data Analytics results drive IC quality & test content optimization?
Auto ICs are no longer N-2 technology — self-driving autos are requiring the latest IC technology.
225th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Title: “Elevating 2D Design And Test To 3D”
Vivek Chickermane
Speaker Biography:
Vivek Chickermane is a Distinguished Engineer at Cadence Design Systems where he is also a Senior Group
Director for R&D in the Modus DFT Software group which is a part of Cadence’s Digital Systems Group. His
professional responsibilities include design and productization of in-system DFT features that are used in high
quality and safety-critical applications. He has been involved in the frontlines of productizing key DFT features such
as OPMISR Compression technology in 2001, IEEE 1149.6 (AC-JTAG) in 2004, IEEE 1500 Core Test Wrapper
synthesis in 2005, development of the first EDA Common Power Format (CPF) in 2008 which could be used by all
tools in an RTL to GDS2 including power-aware test. More recently he and his team have productized 3D IC DFT,
Hierarchical Test Compression using pattern migration, IEEE 1687 (iJTAG) and physically-aware 2D Compression
to reduce the cost of test. Prior to Cadence, Dr Chickermane was at IBM’s Microelectronics Division where he led
the development of the first DFT Synthesis tool in their BooleDozer Synthesis tool which was used in the front-end
of their vector-less ASIC sign-off flow.
Dr Chickermane has published more than 85 technical refereed technical articles and papers and is also a co-inventor
of more than 55 US patents awarded or pending. He serves on several IEEE conference and standards committees
and is currently an Associate Editor of IEEE Design & Test. He received his B.Tech in Electrical Engineering from
Indian Institute of Technology, New Delhi and his M.S and Ph.D degrees in Computer Engineering from the Univ.
of Illinois at Urbana-Champaign.
Abstract:
The city of Bengaluru aka Bangalore has played a prominent role in elevating locally developed technology to
world class status. With its long history of innovation in aerospace, electronics, IT, telecommunications, machine
tooling and many others, Bangalore is the de-facto Tech Capital of India. Inspired by its long historical association
with innovation this presentation will provide some background on the long history of efforts to build multi-chip
modules which is also synonymous with heterogenous integration, 2.5D or 3D packaging. In particular we will
discuss the challenges in the EDA space where efforts to scale solutions that work really well in the flat world have
faced headwinds in moving to the vertical dimension. To make 3D packaging practical requires automation that
spans the widely distributed microelectronics supply chain.
Thankfully we can dip into the reservoirs of 5 decades of technical contributions in design and test of multi-
chip systems and take advantage of modern computational methods and design flows to make 3D integration
technically feasible and cost efficient. This talk will provide some insights into what it will take to elevate the best
practices of current EDA tools to 3D success.
235th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Panel
Discussion
245th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Panel Discussion - ITC India 2021
Title: "Has The Era Of Packetized Scan Architecture
Arrived?"
Abstract:
Number of chip level pins at our disposal to be used for scan testing remains unchanged or is decreasing for the past
several generations of chips. On the contrary, number of scan cells are growing very rapidly as the semiconductor
technology advances to the next smaller node. Moreover, low power design styles and need of advanced fault models
result into unmanageable scan test data volume. In response to these, test community has come up with a variety of
potential solutions such as Streaming Scan Network, USB, PCIe, and Serdes based high speed scan interfaces. One
of the notable developments to address this issue is IEEE 1149.10 Standard for High-Speed Test Access Port and
On-Chip Distribution Architecture.
1. Punit Kishore
Bio: Punit received his B. Tech. (EE) from IIT Kanpur in 2004. He is currently
Engineer, Principal/Mgr at Qualcomm India Private Limited. He currently plays a design
manager role to manage SOC end to end. Prior to design manager at Qualcomm, he has
worked for Texas Instruments, NVIDIA and Intel. Punit has worked in different aspects of
DFT like ATPG, diagnosis, mixed signal DFT, memory testing and repair, IO-DFT, CAD,
Methodology development etc. He has worked extensively in defining automotive DFT
architecture for ADAS and accelerator chips at Qualcomm. He holds 5 USPTO granted
patents in the field of IO-DFT area. He has pioneered USB based testing of SOC.
2. Geir Eide
Bio: Geir is the product management director for the Tessent Design-for-Test products
at Siemens Digital Industries Software. As a 20 year-veteran of the IC DFT and test
industry, Geir has worked with leading semiconductor companies and presented technical
presentations and seminars on DFT, test, and yield learning throughout the world. Geir
earned his MS in Electrical and Computer Engineering from the University of California at
Santa Barbara, and his BS in microelectronics from the University of South-Eastern
Norway.
3. Akshaye Sama
Bio: Akshaye is a Master IC Engineer at Broadcom, where he is responsible for IC test
for DSL line of products. He started his career at Philips Semiconductors designing digital
IPs for TV and mobile SoCs, gaining expertise on most areas of digital IC design. Next was
a deep dive into mixed signal circuits at Texas Instruments developing high speed SerDes
for networking ASICs. During this time he developed an interest in testing for both digital
and analog circuits. Since joining Broadcom in 2009, he has managed SoC DFT for
multiple designs in Broadcom’s Mobile, Set Top Box and Broadband divisions. He holds a
Bachelor of Engineering in Electronics and Communication from MANIT Bhopal(India)
and Masters in VLSI Design from IIT Delhi(India).
255th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
4. Animesh Khare
Bio: Animesh is currently Senior Engineering Manager at Nvidia Graphics,
Bangalore, wherein he manages a team working on In-Field-Test. He has more than 15
years of experience spanning across DFX, architecture, logic design and verification. In
his most recent role, he has architected High Speed Interface based Test Access
Mechanism (TAM) for Nvidia SOC that can be used across Automatic Test Equipment
(ATE), System Level Test (SLT) and In-System-Test (IST). He led end to end
implementation of the TAM and ensured Day-0 silicon bring-up of the feature. His
areas of expertise are In-System-Test ( software, architecture, design, verification) ,
High Speed I/O Test, User Defined Test and Scan Compression. His contribution in the
field of research includes several US patents and publications. Prior to joining Nvidia, he was DFT lead at IBM
System and Technology Group. He has M.Tech in Electronics and Electrical Communication Engineering from
Indian Institute of Technology Kharagpur, India.
5. Denis Martin
Bio: Denis received a B.Sc. degree and a M.Eng. degree both from McGill University,
Montreal, Qc. He joined the Test Automation group at Synopsys, Inc. in the early ’90s. Since
then he has been involved in all aspects of test automation, from scan synthesis and test access,
to ATPG and diagnostics. Presently, he is a Synopsys Scientist and focuses on chip-level access
technologies for manufacturing and in-system test.
Moderator: Kamlesh Pandey
Bio: Kamlesh joined Qualcomm Bangalore in early 2021. He is currently leading
ATPG vertical of Bangalore DFT group. Prior to joining Qualcomm, he has worked at
Broadcom Bangalore for 17 years. At Broadcom he led a team working on DFT
architecture, DFT flow development, DFT implementation on SOCs, ATE bringup
and production support for Settop box and DOCSIS SOCs. Prior to joining Broadcom,
he was DFT engineer at Cisco Systems for 4 years. His contribution in the field of
research includes two US patents and invention of Broadcom in-house at-speed test
architecture known as CTSA. He has received M.Tech. in Microelectronic and VLSI
systems from Indian Institute of Technology Kanpur, in year 2001.
265th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Technical
Sessions
275th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
Session 1 – High Quality Memory Test & Advanced Fault models
1.1 Addressing High Speed Memory Interface Test Quality Gaps in Shared Bus Architecture
Wilson Pradeep, Rajesh Gottumukkala and Srinivas Vooka
Recent trends in high performance SoCs (System-on-Chips) indicate a significant growth in memory
content causing memory paths to be amongst the most critical paths in the designs. Hence, high quality
memory interface tests are crucial in achieving low DPPM (defective parts per million) and better
screening of parts. Shared bus interface is a typical memory architecture used in complex processor cores
to enable memory testing along its true functional access path. In spite of that, certain gaps exist which
limits covering all functional interfaces to memories in its entirety. In this paper, we propose a novel
methodology to strategically identify specific high speed memory interfaces with test quality gaps and
tactically target them through structural scan based tests along the longest path to enable screen for
marginal defects. The proposed method deploys a composite slack based test method to achieve high test
quality at a minimal test cost impact. Experimental results on a large design indicate significant reduction
(67%) in the target fault set, which resulted in 65% reduction in test vectors (71% test time reduction)
using the proposed schemes as compared to baseline methods used for structural memory sequential test.
1.2 Core Test Language based High Quality Memory Testing and Repair Methodology
Puneet Arora, Patrick Gallagher and Steven Gregor
Memories are highly structured and typically consume a large portion of the silicon within a design. As
memories are highly dense and designed to the limits of the technology, they are more prone to failures
than logic. Thus, memories concentrate a large majority of the defects. Several techniques have been
established to target and detect defects within these memory instances and their interfacing logic. The
techniques involve a systematic method of writing and reading data patterns to and from these memory
instances. The IEEE 1450.6.2-2014 standard provides a documented means of describing the information
required to enable memory built-in self-test (MBIST) hardware insertion and connection to the memories
under test while providing the capability to utilize the most advanced memory testing techniques to test,
perform failure analysis and, when redundant resources exist, repair these memories. MBIST models which
strictly adhere to the IEEE 1450.6.2-2014 standard will enable EDA tool independence and provide
consistent quality across all platforms. This paper describes some aspects of this standard and the
challenges faced by memory providers, the producers of these models, while creating standard compliant
MBIST models. The paper also describes the advantages of generating standard compliant MBIST models
from the SoC designer and design implementation point of view along with MBIST tool providers,
consumers of these models. The paper describes the Cadence Design Systems, Inc. environment
comprising Genus, Modus, Xcelium and some standard utilities to enable the generation and validation of
these views.
285th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
1.3 Targeting Zero DPPM through Adoption of Advanced Fault Models and Unique Silicon Fall-out
Analysis
Aravinda Acharya, Nikita Naresh, Prakash Narayanan, Rubin Parekhji, Wilson Pradeep, Kevin Roush,
Humberto Ibarra, Raj Sheth and Clarence Flora
The test of digital circuits has benefitted greatly from the adoption of logical fault models and automatic
test pattern generation (ATPG) tools targeting them. The cyclic process of defects in newer technology
nodes being increasingly missed out by gross fault models and newer fault models being developed to
better target them in silicon has continued, and EDA tools have evolved to provide new automation
capabilities. This paper presents silicon results on one of Texas Instruments’ new safety critical products
which show unique defect detection with patterns targeting newer fault models like small delay defects
(SDD) and cell aware faults (CAF), and RAM Sequential (RAM-S) ATPG patterns for memory faults. The
net defective parts per million (DPPM) recovered using these methods is 72. Based on these results,
recommendations for coverage targets and the order in which these faults must be targeted are provided.
The unique silicon fall-out data presented in this paper provides a strategy for very low (zero) DPPM test
of digital systems-on-chips (SoCs) in advanced technology nodes.
Session 2 – Functional Safety & Hardware Security
2.1 Parallel Field Test Architecture for Boot-ROMs in Safety-Critical SoCs
Nitesh Mishra, Nikita Naresh and Aravinda Acharya
In safety-critical automotive devices with functional Read-only-memories (ROMs), boot-up time and
periodic check of correctness of the ROM code is of utmost importance for the overall operation of the
device from safety perspective. Current solutions use a hardware/software Cyclic Redundancy Check
(CRC) to validate the ROM contents. However, CRC comes with a significant test time overhead, which
can impact the boot-up time of device. In this paper, we present a novel non-destructive field-test
architecture which validates the ROM contents parallelly and reduces test-time significantly by 99% as
compared to native CRC. We also present a novel methodology using which we can perform parallel test
on boot-ROMs without disturbing the boot flow during power-up.
2.2 Comprehensive In-field Memory Self-Test and ECC Self Checker –Minimal Hardware Solution
for FuSa
Ratheesh Thekke Veetil, Ramesh Sharma and Swapna Gundeboyina
As technology advances and System on Chip (SoC) become more complex, more and more embedded
memories are packed inside the SoCs to cater the system requirements. Probability of malfunctioning of the
device infield due to soft or hard defects in these memories and associated circuitry increase proportionally
as well. As a result, in addition to testing and screening the product during manufacturing stage, the need
for in-field testing of the memories has become critical to address Functional Safety (FuSa) requirements in
mission critical industries such as automotive, medical and Artificial Intelligence (AI). In general, on most
SoCs, Error Correcting Code (ECC) or parity checking schemes are implemented to detect and correct the
error during memory access. Ensuring the correctness of the ECC operation in-field is also a safety critical
requirement.
295th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
2.3 Side-channel Analysis for Hardware Trojan Detection using Machine Learning.
Shuo Yang, Prabuddha Chakraborty and Swarup Bhunia
The evolving trend of the semiconductor supply chain resulted in a wide array of trust issues for electronic
hardware. Among them, malicious alteration of designs in an untrusted design house or foundry, also
known as hardware Trojan insertion, has emerged as a serious concern. A popular countermeasure against
hardware Trojan attacks relies on identifying a Trojan fingerprint in a side-channel parameter. However,
side-channel analysis suffers from (1) the process variations introduced in chips during fabrication and (2)
the inability of conventional techniques to detect side-channel signatures of a small Trojan in a large
design. In this paper, we propose a machine learning approach to detect malicious Trojan activities in a
chip with high sensitivity. We use a custom-designed circuit board and measurements from several Trojan-
inserted test chips for validating our proposed technique. We were able to detect Trojans with very high
confidence and precision. Our method could detect extremely small Trojans of size as small as four gates
with over 80% confidence. For larger Trojans, the prediction confidence is above 99%. We have also
devised and implemented a framework for time-efficient automatic testing of a target chip using our
method.
Session 3 – Best Practices in Accelerated Pre-Silicon Verification,
Analog & Stress Testing
3.1 Accelerating GLS Simulation closure in DFT with Emulator Hardware
Kriti Das, Padmini Prakash and Abhimanyu Zala
To keep pace with the demands of advanced complex SoC development and to close the HW/SW
verification gap, Emulation is increasingly used as a scalable and reusable solution. As part of a quicker
execution schedule, DFT Engineers deploy optimum methods of RTL, ATPG, MBIST verification, and
even proto-type complete RTL into Emulator for faster RTL verification closure. Another integral part of
DFT verification is Gate-Level Simulation of MBIST and ATPG patterns but done in small volume due to
huge simulator-time requirement leading to incomplete closure. We propose vectormode based Gate level
emulation (GLE) for DFT patterns. This paper talks about 500-to-1500X performance gain when
simulating MBIST and ATPG complete pattern set in Emulator over GLS. Results show that for 2 SOCs of
size 36M, 55M gates, a complete stuck-at, and transition ATPG WGL format pattern set of 90k can be
simulated in Emulator within hours. Manufacturing Algorithm-based MBIST WGL patterns which take
weeks in the EDA simulator can be emulated in minutes. This provides closure of DFT Pre-silicon GLS
Verification within a day. The verified WGL patterns can be seamlessly ported to ATE Tester program for
post-silicon Bring-up, bridging the verification gap between RTL and silicon device. The paper also shows
a method of debugging ATPG and MBIST pattern failures with debug logs and waveforms dumped from
the Emulator program.
305th IEEE International Test Conference India (ITC India) 2021
July 18-20, 2021
3.2 Method and Apparatus for Bug Free Rapid Silicon Bringup
Ravikumar Patel, V N Sivakumar Avvaru, Ashutosh Anand, Kirankumar Tatti, Prakash Kumar and
Shokhi Rastogi
Today SoC designs are complex and dense with millions of transistors. These designs have complex DFT
architecture for testing. Thousands of DFT patterns are used during silicon bring up. All these patterns are
going through multiple stages of pre silicon verification to ensure bug free design and meet higher pass rate
on silicon. In this paper, we will talk about DFT pre silicon validation flow enhancements at different
stages to verify design quality and ensure patterns quality delivered for post silicon validation with
maximum patterns passing without re-generation in short duration of post silicon testing. This paper talks
about enhancement done across different stages of verification cycle to meet rapid silicon bringup with
zero post silicon DFT bugs.
3.3 A Novel Method to measure PLL Bandwidth in a 5G RF transceiver
Pradeep Nair and Dineej A
Integrated PLLs are, nowadays, a part of all high-performance RF SoCs. This is required due to increasing
system bandwidth requirement with every generation of wireless transceivers. The analog front-end
converters (ADC and DACs) need to be clocked at higher clock rate. Some transceiver architectures
involve analog mixers which also involve high frequency clock generation. Integrated On-Chip PLLs are
needed for sampling clock or mixer clock generation for these systems. PLL uses a feedback control loop
to lock the phase of the internal voltage-controlled oscillator with an incoming low frequency reference
clock. The bandwidth of the loop filter used in the PLL is important to ensure the noise performance of
PLL. Measuring the PLL bandwidth is not easy without extra DFT blocks and dedicated test points. If the
RF transceiver has multiple analog PLLs, this can be difficult. This paper proposes a non-intrusive method
to measure PLL bandwidth in RF transceivers.
3.4 An Efficient Test Architecture for Concurrent Over Voltage Stress Testing (OVST) of Logic and
Memory
Snehil Agrawal, Kamlesh Pandey, Ravi Chandra Kumar Y and Anurag Jain
Many of the latent defects in modern day SoCs don’t get activated at the time of final package tests carried
out under Adaptive Voltage Scaling (AVS) and rated functional operating frequencies. As a result, chips
with latent defects too pass the final package testing. The latent defects become active during initial period
of operation in the field causing serious long term reliability issues. High voltage stress tests, when
deployed methodically accelerate the chip ageing and are quite efficient in exposing latent defects that lead
to early life failures or infant mortality. It helps in catching unreliable parts before they are shipped to the
customers. For set-top box SoCs, Overvoltage stress test (OVST) is performed at 1.4x of nominal device
operating voltage for a duration of 200ms to 400ms. The desirable toggle coverage for logic and memories
is 85% or greater to expose majority of the potential latent defect sites. These parameters can vary for
different product lines and are arrived at by carefully using a robust methodology touched upon in this
paper. This paper demonstrates how a JTAG pins based low pin count scan test infrastructure can be
leveraged to achieve 85% toggle coverage across the entire digital portion of the SoC. The OVST
architecture ensures all the memories are active along with logic thus both are tested concurrently in a
single test. This scheme eliminates separate logic and memory OVST tests culminating into less than one-
fourth of original test-time and avoids excessive over stressing of the device.
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