Write operation study of Co/BTO/LSMO ferroelectric tunnel junction
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Write operation study of Co/BTO/LSMO ferroelectric tunnel junction Z. H. Wang, W. S. Zhao, W. Kang, A. Bouchenak-Khelladi, Y. Zhang et al. Citation: J. Appl. Phys. 114, 044108 (2013); doi: 10.1063/1.4816474 View online: http://dx.doi.org/10.1063/1.4816474 View Table of Contents: http://jap.aip.org/resource/1/JAPIAU/v114/i4 Published by the AIP Publishing LLC. Additional information on J. Appl. Phys. Journal Homepage: http://jap.aip.org/ Journal Information: http://jap.aip.org/about/about_the_journal Top downloads: http://jap.aip.org/features/most_downloaded Information for Authors: http://jap.aip.org/authors Downloaded 12 Sep 2013 to 129.175.97.14. This article is copyrighted as indicated in the abstract. Reuse of AIP content is subject to the terms at: http://jap.aip.org/about/rights_and_permissions
JOURNAL OF APPLIED PHYSICS 114, 044108 (2013)
Write operation study of Co/BTO/LSMO ferroelectric tunnel junction
Z. H. Wang,1,2 W. S. Zhao,1,2,a) W. Kang,1,2 A. Bouchenak-Khelladi,1,2 Y. Zhang,1,2
J.-O. Klein,1,2 D. Ravelosona,1,2 and C. Chappert1,2
1
IEF, Univ. Paris-Sud XI, Orsay 91405, France
2
UMR 8622, CNRS, Orsay 91405, France
(Received 6 June 2013; accepted 8 July 2013; published online 29 July 2013)
Recently, a Co/BaTiO3/La0.67Sr0.33MnO3 (Co/BTO/LSMO) ferroelectric tunnel junction (FTJ) has
shown the great potential towards non-volatile memory and logic applications due to its excellent
performance. Especially, the giant OFF/ON tunnel resistance ratio (e.g., 100) assures that FTJ-
based random access memory (FTRAM) can achieve lower reading error rate than emerging
magnetic RAM. Nevertheless, in this paper, our investigation demonstrated that this FTJ suffered
from difficulties in write operation when integrating with current CMOS technology into a FTRAM.
Specifically, the write performances of Co/BTO/LSMO 1T1R FTRAM such as cell area, speed,
energy dissipation, and thermal fluctuation effect were simulated and evaluated with a compact
model and CMOS 40 nm design kit. Simulation results indicate the drawbacks of this FTRAM
including significant performance asymmetry between two write orientations, high write voltage,
large cell area, and severe thermal fluctuation disturbance. Simultaneously, this research provides
several methods of improving write performance of FTRAM from the perspective of device size
and process parameters. V C 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4816474]
I. INTRODUCTION example with CMOS 40 nm design kit.14 Second, related
models for devices and circuits are proposed to assist the per-
Emerging ferroelectric tunnel junction (FTJ)1,2 has
formance analysis. Then the simulation results on write per-
attracted intense interest of the research organizations due to
formances such as speed and energy are presented and
its great potential applications in non-volatile memory and
evaluated. Finally, we present conclusions and perspectives
logic (NVM and NVL).3 Especially, since the critical thick-
for this work.
ness of ferroelectric thin film was shrunk to only a few unit
cells in the past decade,4,5 masses of experimental prototypes
II. STRUCTURE AND RELATED MODELS
have been reported,6–12 making progresses towards the com-
mercialization of FTJ-based random access memories The schematic structure of Co/BTO/LSMO FTJ is
(FTRAMs). Among them, a Co/BaTiO3/La0.67Sr0.33MnO3 shown in Fig. 1(a), where a ferroelectric ultrathin film is
(Co/BTO/LSMO) FTJ was announced to exhibit experimen- sandwiched between two different electrodes. The ferroelec-
tally excellent non-volatile performances.8,9 In our recent pa- tric ultrathin film has two different spontaneous polarization
per,13 a compact model for this Co/BTO/LSMO FTJ was directions which can be switched by applying bias voltage.
proposed and programmed in Verilog-A language on Cadence The switching of polarization direction induces the modula-
Platform. By simulation with this model, we demonstrated tion on profile of tunnel barrier potential,15–17 giving rise to
that FTRAM promises to achieve much more reliable readout two different tunnel resistance states [see Fig. 1(b)].
than other NVMs based on purely electronic mechanisms To build up FTRAM, the classical 1T1R memory cell18
thanks to its larger OFF/ON tunnel resistance ratio, i.e., TER is designed with a MOS transistor, a FTJ nanopillar, a word
ratio (e.g., 100). In this present paper, our works are focused line (WL), a bit line (BL), and a source line (SL), as illus-
on the write operation study of this Co/BTO/LSMO FTJ. trated in Fig. 2(a). FTRAM consisting of this cell array is
Based on classical 1T1R cell structure, we simulated system- shown in Fig. 2(b), where the WLs control the permission of
atically the write performances of a FTRAM and analyzed write operation, the BLs and SLs are used to produce dual-
their dependences on device/process parameters. Our simula- direction write voltage by applying different voltage levels.
tion results indicate that, in contrast to high reliable readout, As other non-volatile technology,19 FTJ can be integrated in
this FTJ fails to show competitive write performances when the back-end process above the CMOS circuits, thereby the
integrating with current CMOS technology into FTRAM. cell area of 1T1R structure is mainly determined by size of
Evaluation of simulation results provides instructive sugges- MOS transistor.
tions for the optimization of FTRAM. For performance simulation and evaluation, a compact
This paper is organized as follows: first, a FTRAM array spice-compatible model for Co/BTO/LSMO FTJ has been
based on the classical 1T1R memory cell is designed as developed and shown good agreement with experimental
measurements.13 Here, we briefly introduce physical descrip-
tion of this model related to write operation. Table I lists pa-
a)
Author to whom correspondence should be addressed. Electronic mail: rameters used in the following context (default values
weisheng.zhao@u-psud.fr correspond to experimental measurements).8,9
0021-8979/2013/114(4)/044108/6/$30.00 114, 044108-1 C 2013 AIP Publishing LLC
V
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e2 m jV D/j2
I ¼ Area BTO 2
16p2 hmBTO /t
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !
4 2emBTO / 3=2
exp tBTO ; (3)
3h jV D/j
where I is current, V is applied bias voltage, and
mBTO ¼ 6.5 m is the effective electron mass in BaTiO3 bar-
rier.22 The descriptions of other parameters are shown in
Table I. Note that this modified model takes into account the
asymmetry of I-V curve, i.e., D/ 6¼ 0.
FIG. 1. (a) Schematic viewgraph of a Co/BTO/LSMO FTJ: ferroelectric ultra-
thin film BaTiO3 sandwiched between Co and La0.67Sr0.33MnO3. NdGaO3 is
The write operation of FTJ is described by KAI
used as substrate. (b) Typical I-V curve of this FTJ in DC simulation. model23,24 and Merz’s Law25,26 in the following equations:
( " #)
t sN 2
DPðtÞ ¼ 2Ps hðt sN Þ 1 exp ; (4)
At low bias voltage, the tunnel resistance of FTJ is cal- sP
culated by Brinkman model20 in the following equations:
pffiffiffi EaN;P
tBTO 1=2 ; sN;P ¼ s0N;P exp
Rð0Þ ¼ exp 2 2 A t BTO / (1) E
1=2 Area
F1 /
UN;P E0
¼ s0N;P exp tBTO ; (5)
kB T V
Rð0Þ
R¼ ; (2)
A tBTO D/ A2 tBTO 2 2 where DP(t) denotes polarization change, Ps is spontane-
1 V þ V
3=2
F2 / F3 / ous polarization, h(t) is Heaviside step function, V is the
applied bias voltage, and EaN,P ¼ UN,PE0/(kBT) is called
where R(0) is the resistance of FTJ under zero bias voltage, R activation field. In our simulation, it is defined that
is the real resistance of FTJ during operation, A ¼ (me)1/2/h the switching is finished when DP(t) 99.8%, thereby
is a constant, and V is the applied bias voltage. the write delay (s) is calculated by the following
However, experimental measurements9 demonstrated equation:
that a Co/BTO/LSMO FTJ with 2 nm thick barrier should be
applied to 4 V to achieve write operation as fast as 10 ns. s ¼ sN þ 2:5sP : (6)
So large bias voltage possibly causes other transport mecha-
nisms (e.g., Fowler-Nordheim tunneling,21 charge transfer, TABLE I. Parameters for FTJ nanopillar model [HRS: High Resistance
and lattice distortion) contributing to current in FTJ, which State; LRS: Low Resistance State].
makes this issue rather complicated. By comparison with ex-
perimental data, Brinkman equation is employed for our sim- Parameter Description Default value
ulation at high bias voltage. Take a HRS FTJ with 200 nm
tBTO BTO film thickness 2 nm
diameter and 2 nm thick barrier, for example, at a write volt- Area Tunnel junction area p (100 nm)2
age of 4 V, from a modified Fowler-Nordheim tunneling
/ Average potential barrier height HRS: 0.9 eV
model21 shown in Eq. (3), the write current is 26 lA, while LRS: 0.5 eV
it is 22 lA from Brinkman equation, closer to experimental D/ Potential height difference HRS: 0.15 eV
result of 6 lA9 between the two boundaries LRS: 0.1 eV
of BTO barrier
F1 Factor calculated from resistance-area 1.87 105
product of FTJ
F2 Fitting factors determined by HRS: 0.385
experimental measurement LRS: 0.989
HRS: 1.68
F3 LRS: 6.70
T Temperature 300 K
UN Creep energy barrier for nucleation 0.67 eV
UP Creep energy barrier for propagation 0.52 eV
E0 Characteristic field 1 GV/m
s0N Attempt time of nucleation 2.8 1015 s
s0P Attempt time of propagation 9 1014 s
m Electron mass 9.11 1031 kg
e Elementary charge 1.6 1019 C
FIG. 2. (a) Structure of memory cell, (b) cell array image. Note that we only
h Plank’s constant 1.054 1034 J s
show those modules related to write operation in this figure, and sensing am- kB Boltzmann constant 1.38 1023 J/K
plifier is omitted.
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In 1T1R cell structure, the write voltage (Vw) and the
write current (Iw) applied to FTJ nanopillar can be roughly
evaluated by the following equations:
RFTJ
Vw ffi jVBL VSL j; (7)
RFTJ þ RMOS
jVBL VSL j
Iw ffi ; (8)
RFTJ þ RMOS
where VBL and VSL are the voltages of bit line and source
line, respectively, RFTJ and RMOS are resistances of FTJ
nanopillar and MOS transistor, respectively.
In order to supply large enough write voltage for FTJ
nanopillar, the MOS transistor should operate in linear
region; in this case, the resistance of MOS transistor can be
approximately described by the following equation:27
1
RMOS ¼ ; (9)
ln Cox ðW=LÞ ðVgs Vth Þ
where ln is the electron mobility, Cox is the gate oxide ca-
pacitance per unit area, W and L is the channel width and
length, respectively, Vgs is the gate-source voltage, and Vth is
the threshold voltage of the MOS transistor.
With these models and CMOS 40 nm design kit, write
FIG. 3. The comparison of write performance (speed and energy) under dif-
simulation of Co/BTO/LSMO FTRAM can be performed on
ferent operation voltages. (a) and (b) Write speed and energy when writing
Cadence Platform. Write performances such as cell area, “0”; (c) and (d) write speed and energy when writing “1.” During simulation,
speed, and energy can be analyzed by combining the simula- the parameters of FTJ is set to default values shown in Table I, and MOS
tion results and theoretical models. The write energy dissipa- transistor channel width/length is set to minimum size, i.e., 0.5 lm/1.2 lm.
tion per bit (Ew) can be calculated by the following equation:
ðs
Ew ¼ jVBL VSL j Iw ðtÞ dt; (10) FTRAM. However, excessive high operation voltage
0
increases the risk of breakdown for CMOS circuits. In our
where the descriptions of these parameters are identical to following simulation, the operation voltage is set to 4.5 V for
those appeared in Eqs. (6)–(8). VWL and 4.2 V for jVBL-VSLj as representative example.
Actually 4 V is a dangerous voltage for CMOS 40 nm
technology node, therefore, we have to adopt special MOS
III. RESULTS AND DISCUSSIONS
transistor with thicker oxide layer and larger channel area to
A. Operation voltage ensure reliability.12 This is an essential reason why the inte-
gration between Co/BTO/LSMO FTJ and current CMOS
First of all, the operation voltage of FTRAM is investi-
technology is limited.
gated and determined in this subsection. Considering a write
voltage of 4 V for a write delay of 10 ns, we choose sev-
B. FTJ size
eral voltages around 4 V for simulation, and corresponding
results are shown in Fig. 3. Two conclusions are drawn from Fig. 4 demonstrates the write performance as a function
these simulation results. of surface diameter (or junction area) under different barrier
First, both speed and energy display high asymmetry thicknesses. It is seen that both the write speed and energy
between writing “0” (switching from LRS to HRS) and writ- are optimized by reducing the junction area. This result can
ing “1” (switching from HRS to LRS). Typically, writing be justified by a series of theoretical models: first, from Eq.
“0” show much poorer performance than writing “1” (e.g., (1) the resistance increases when the junction area decreases,
ls vs. ns in speed and nJ vs. pJ in energy). This char- then write voltage increases and write current decreases [see
acteristic is attributed to higher TER ratio of FTJ (as high as Eqs. (7) and (8)], resulting in higher write speed and lower
100 when 2 nm barrier according to Eq. (1)). Equations (7) write energy [see Eqs. (5) and (10)].
and (8) indicate that larger TER ratio leads to more signifi- However, the comparison of results shows that reducing
cant difference of write voltage and current between two the barrier thickness hardly optimizes the write performance,
writing orientations, giving rise to larger performance gap in although Eq. (5) predicts that thinner barrier speeds up write
speed and energy [see Eqs. (5) and (10)]. operation. This is explained as follows: reducing barrier
Second, increasing operation voltage (both VWL and thickness leads to decrease of tunnel resistance [see Eq. (1)],
jVBL-VSLj) can optimize the write speed and energy of thereby write voltage decreases [see Eq. (7)] and write
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FIG. 4. The dependence of write performance on FTJ diameter while barrier
thickness is 2 nm and 1.6 nm. (a) Simulation results when writing “0”; (b) FIG. 6. The simulation results of write performance recorded in different
simulation results when writing “1.” During simulation, other parameters are temperatures ranged from 275 K to 340 K, illustrating the effect of thermal
set to default values as mentioned in Fig. 3. fluctuation. (a) Results when writing “0,” (b) results when writing “1.” Other
parameters are set to default values as mentioned in Fig. 3.
current increases [see Eq. (8)]. It is mainly this change in
voltage and current that influences the write performance. In increases while write delay decreases. We infer that decreas-
Eq. (5), the write voltage decays faster than barrier thickness ing write delay is more prominent factor as simulation results
due to exponential dependence of tunnel resistance on barrier show the decrease of write energy.
thickness [see Eq. (1)], thereby write speed decreases. As a In addition, note that the write performance when writing
result, the multiple increase in write current and write delay “0” is more sensitive to variation of cell area than that when
together produce soaring write energy [see Eq. (10)]. writing “1.” For instance, during the simulation, the speed
In summary, from the perspective of FTJ size, miniaturiza- varies by 500% and energy varies by 300% when writing
tion of junction area is an efficient method of optimizing write “0,” but only 50% and 20%, respectively, when writing
performance of FTRAM. For instance, for FTJ with 2 nm bar- “1.” This confirms that LRS FTJ is more easily influenced by
rier thickness, the write speed and energy can attain044108-5 Wang et al. J. Appl. Phys. 114, 044108 (2013)
FIG. 9. The simulation results of write performance under lower operation
FIG. 8. (a) The write delay versus creep energy barrier at 295 K and 305 K, voltages while the creep energy barrier is decreased to 0.6 eV and 0.45 eV.
and here we only show the results for writing “0,” (b) the ratio of delay vari- Here, we only show simulation results for writing “0.” Other parameters are
ation versus creep energy barrier. In simulation, we vary simultaneously UN set to default values as mentioned in Fig. 3.
and UP, and keep UN-UP ¼ 0.15 eV. Other parameters are set to default val-
ues as mentioned in Fig. 3.
attain similar performance (1.5 ls in delay and 1.5 nJ in
energy) to that under VWL ¼ 4.5 V and jVBL-VSLj ¼ 4.2 V.
magnitude of ratio shown in Eq. (11), fluctuation of 10 K However, it should be noted that excessive low creep
causes performance variation as high as 60% when write “0” energy barrier is disadvantageous to maintain long-time data
retention in FTRAM. It was experimentally observed that
sL sH the polarization stored in ferroelectric thin film decays with
Ratio ¼ ; (11)
sH time due to depolarization field and redistribution of oxygen-
vacancy.28,29 The retention time (tr) is defined as an upper
where sL and sH are the write delay at lower temperature and limit of time at which the ferroelectric polarization decays so
higher temperature, respectively. In our simulation, the two low that it fails to be successfully detected by sense ampli-
temperatures are set to 295 K and 305 K. fier. Depending on different failure mechanisms,30–32 tr can
Inspired by conclusions in Secs. III B and III C, we infer be evaluated by Arrhenius reaction model or logarithmic
that thermal fluctuation disturbance can be alleviated by polarization decay model by the following equations:
adjusting the FTJ size or cell area. As expected, Fig. 7
DE
shows that reducing the junction area or increasing cell area log tr ¼ þ const; (12)
kB T
enhances immunity against thermal fluctuation, however,
reducing barrier thickness aggravates the thermal fluctuation
tr DE
disturbance. Equation (5) can explain these results as it log log ¼ þ const; (13)
t0 kB T
show that thermal fluctuation disturbance is controlled by
write voltage. Variation of FTJ size and cell area can lead to where t0 is characteristic time and DE is activation energy
increase or decrease of write voltage, as analyzed in Secs. responsible for failure. Both in Eqs. (12) and (13), activa-
III B and III C. tion energy DE is proportional to creep energy barrier
(DE / UN;P ).33,34 Therefore, lower creep energy barrier can
E. Creep energy barrier reduce the retention time of FTRAM.
Activation field (Ea) [see Eq. (4)] is a crucial experimen-
tal parameter determining the switching behavior of FTJ. In IV. CONCLUSIONS AND PROSPECTIVES
this subsection, we evaluate the role of activation field by
We have simulated and analyzed the write performance
varying the creep energy barrier (UN and UP). Fig. 8(a)
of Co/BTO/LSMO FTRAM based on 1T1R cell structure.
shows the write delay as a function of creep energy barrier at
Our results validate that the integration between this Co/BTO/
different temperatures. Results demonstrate that write speed
LSMO FTJ and CMOS technology is still limited under cur-
is improved by decreasing the creep energy barrier, as
rent fabrication process. Limitations are detailed as follows.
expected by Eq. (5). Moreover, from Eq. (5), thermal fluctua-
tion disturbance is reduced by decreasing creep energy bar- (a) Significant performance asymmetry between writing
rier, validated by simulation results shown in Fig. 8(b). “0” and writing “1,” which is also a fundamental prob-
Also the creep energy barrier is closely related to opera- lem encountered by other non-volatile memories with
tion voltage. In Fig. 9, we choose a series of operation vol- high OFF/ON resistance ratio.
tages for simulation under UN ¼ 0.6 eV and UP ¼ 0.45 eV, (b) High operation voltage (4 V), hindering integration
which are lower than default values [see Table I]. Comparison with CMOS 40 nm technology node.
of results demonstrates that operation voltage promises to be (c) Large cell area (1 lm2), limiting the memory density.
decreased by reducing creep energy barrier. For instance, (d) Sensitive to thermal fluctuation, injuring the stability
when write “0” just VWL ¼ 3.6 V and jVBL-VSLj ¼ 3.4 V can of memory.
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