Nios Embedded Processor - Hardware Tutorial
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Nios™ Embedded Processor
Hardware Tutorial
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.comNios Embedded Processor Hardware Tutorial Version 1.0 November 2000 Altera, the Altera logo, and MAX+PLUS II are registered trademarks of Altera Corporation in the United States and other countries. AMPP, APEX, APEX 20K, APEX 20KE, Atlas, BitBlaster, ByteBlaster, ByteBlasterMV, MasterBlaster, MegaLAB, MegaWizard, EP20K100, Quartus, and the Quartus logo are trademarks and/or service marks of Altera Corporation in the United States and other countries. Product design elements and mnemonics used by Altera Corporation are protected by copyright and/or trademark laws. Altera Corporation acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, including the following: Microsoft is a registered trademark and Windows and Windows NT are trademarks of Microsoft Corporation. Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty. Testing and other quality control techniques are used to the extent Altera deems such testing necessary to support this warranty. Unless mandated by government requirements, specific testing of all parameters of each device is not necessarily performed. In the absence of written agreement to the contrary, Altera assumes no liability for Altera applications assistance, customer’s product design, or infringement of patents or copyrights of third parties by or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent right, copyright, or other intellectual property right of Altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. Altera products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Altera Corporation. As used herein: 1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Products mentioned in this document are covered by one or more of the following U.S. patents: 5,915,017; 5,909,450; 5,909,375; 5,909,126; 5,905,675; 5,904,524; 5,900,743; 5,898,628; 5,898,318; 5,894,228; 5,893,088; 5,892,683; 5,883,526; 5,880,725; 5,880,597; 5,880,596; 5,878,250; 5,875,112; 5,873,113; 5,872,529; 5,872,463; 5,870,410; 5,869,980; 5,869,979; 5,861,760; 5,859,544; 5,859,542; 5,850,365; 5,850,152; 5,850,151; 5,848,005; 5,847,617; 5,845,385; 5,844,854; RE35,977; 5,838,628; 5,838,584; 5,835,998; 5,834,849; 5,828,229; 5,825,197; 5,821,787: 5,821,773; 5,821,771; 5,815,726; 5,815,024; 5,815,003; 5,812,479; 5,812,450; 5,809,281; 5,809,034; 5,805,516; 5,802,540; 5,801,541; 5,796,267; 5,793,246; 5,790,469; 5,787,009; 5,771,264; 5,768,562; 5,768,372; 5,767,734; 5,764,583; 5,764,569; 5,764,080; 5,764,079; 5,761,099; 5,760,624; 5,757,207; 5,757,070; 5,744,991; 5,744,383; 5,740,110; 5,732,020; 5,729,495; 5,717,901; 5,705,939; 5,699,020; 5,699,312; 5,696,455; 5,693,540; 5,694,058; 5,691,653; 5,689,195; 5,668,771; 5,680,061; 5,672,985; 5,670,895; 5,659,717; 5,650,734; 5,649,163; 5,642,262; 5,642,082; 5,633,830; 5,631,576; 5,621,312; 5,614,840; 5,612,642; 5,608,337; 5,606,276; 5,606,266; 5,604,453; 5,598,109; 5,598,108; 5,592,106; 5,592,102; 5,590,305; 5,583,749; 5,581,501; 5,574,893; 5,572,717; 5,572,148; 5,572,067; 5,570,040; 5,567,177; 5,565,793; 5,563,592; 5,561,757; 5,557,217; 5,555,214; 5,550,842; 5,550,782; 5,548,552; 5,548,228; 5,543,732; 5,543,730; 5,541,530; 5,537,295; 5,537,057; 5,525,917; 5,525,827; 5,523,706; 5,523,247; 5,517,186; 5,498,975; 5,495,182; 5,493,526; 5,493,519; 5,490,266; 5,488,586; 5,487,143; 5,486,775; 5,485,103; 5,485,102; 5,483,178; 5,477,474; 5,473,266; 5,463,328, 5,444,394; 5,438,295; 5,436,575; 5,436,574; 5,434,514; 5,432,467; 5,414,312; 5,399,922; 5,384,499; 5,376,844; 5,371,422; 5,369,314; 5,359,243; 5,359,242; 5,353,248; 5,352,940; 5,309,046; 5,350,954; 5,349,255; 5,341,308; 5,341,048; 5,341,044; 5,329,487; 5,317,210; 5,315,172; 5,301,416; 5,294,975; 5,285,153; 5,280,203; 5,274,581; 5,272,368; 5,268,598; 5,266,037; 5,260,611; 5,260,610; 5,258,668; 5,247,478; 5,247,477; 5,243,233; 5,241,224; 5,237,219; 5,220,533; 5,220,214; 5,200,920; 5,187,392; 5,166,604; 5,162,680; 5,144,167; 5,138,576; 5,128,565; 5,121,006; 5,111,423; 5,097,208; 5,091,661; 5,066,873; 5,045,772; 4,969,121; 4,930,107; 4,930,098; 4,930,097; 4,912,342; 4,903,223; 4,899,070; 4,899,067; 4,871,930; 4,864,161; 4,831,573; 4,785,423; 4,774,421; 4,713,792; 4,677,318; 4,617,479; 4,609,986; 4,020,469; and certain foreign patents. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Copyright © 2000 Altera Corporation. All rights reserved.
Table of Contents
Tutorial Overview ............................................................................................1
Tutorial Files.......................................................................................2
Design Entry.....................................................................................................3
Create a Quartus Project ..........................................................................3
1. Start the Quartus Software ............................................................3
2. Create a Project...............................................................................3
Create a Nios System Module..................................................................5
1. Create a New Block Design File.....................................................5
2. Create the Nios Embedded Processor ..........................................6
3. Create & Memory Map System Peripherals .................................8
Create the boot_monitor_rom System Peripheral ................9
Create the ext_flash & ext_ram System Peripherals ........10
Create the button_pio, lcd_pio, led_pio &
seven_seg_pio System Peripherals......................................14
Create the uart1 System Peripheral .......................................17
Create the timer1 System Peripheral.....................................19
4. Configure System Module Settings.............................................20
5. Synthesize the Design with LeonardoSpectrum Software........21
6. Enter Input, Output, Bidirectional & Primitive Symbols ..........23
7. Name the Pins...............................................................................26
8. Connect the Pins ..........................................................................29
Compilation ...................................................................................................33
Create Compiler Settings .......................................................................33
1. View the Compiler General Settings ...........................................33
2. Specify the Device Family & Device............................................34
Assign Signals to Device Pins.................................................................36
1. Assign Pins with a Tcl Script........................................................36
2. Verify the Pin Assignments..........................................................37
Specify Device, Programming & EDA Tool Settings ............................38
1. Reserve Unused Pins....................................................................39
2. Specify Optional Programming Files..........................................39
3. Specify EDA Tool Settings............................................................40
Compile the Design ................................................................................40
Programming .................................................................................................43
Configure an APEX Device.....................................................................43
Download the Design to Flash Memory ...............................................46
1. Start the bash Shell.......................................................................47
2. Run the Sample hello.srec Test Program ...................................48
3. Download the Configuration Data to Flash Memory................49
Restore Factory Default Configuration.................................................52
Contacting Altera ...........................................................................................54
Technical Support............................................................................54
iiiNios Embedded Processor Hardware Tutorial
Product Information........................................................................ 54
ivTutorial Overview
This tutorial introduces you to the Nios™ embedded processor. It shows
you how to use the Quartus™ software to create and process your own Nios
embedded processor design that interfaces with components provided on
the Nios development board.
The sections in this tutorial guide you through the steps necessary to
create, compile, and download a 32-bit Nios embedded processor design,
called nios_system_module. A Nios system module is composed of a Nios
embedded processor and its associated system peripherals and
interconnections.
After you create the nios_system_module design, you can download it into
an Altera® APEX™ device. When you download the design to the device, the
system module pins are logically connected to pins on the APEX device.
The external physical pins on the APEX device are in turn connected to
other hardware components on the Nios development board, allowing the
Nios embedded processor to interface with RAM, flash memory, LEDs,
LCDs, switches, and buttons.
The tutorial is divided into the following three sections:
■ “Design Entry” on page 3 teaches you how to create the Nios system
module in a Block Design File (.bdf) using the MegaWizard Plug-In
Manager™ - Nios System Builder. This section also teaches you how
to connect the system module ports to pins in the APEX device.
■ “Compilation” on page 33 teaches you how to compile the Nios
embedded processor system module using Compiler settings, pin
assignments, and EDA tool settings to control compilation
processing.
■ “Programming” on page 43 teaches you how to use the Quartus
Programmer and the ByteBlasterMV™ cable to download the design
to an APEX device. It also teaches you how to download the design to
a flash memory device provided on the Nios development board.
Altera Corporation 1Nios Embedded Processor Hardware Tutorial
1 This tutorial assumes that you have completed the following
prerequisite items:
■ Installed the following software on a PC:
– Quartus software version 2000.05, with support for
the APEX EP20K200E device, as described in the
Quartus Installation and Licensing for PCs manual
– Exemplar Logic LeonardoSpectrum software
version 1999.1j licensed for Verilog HDL. If you have
a VHDL license, replace references to Verilog HDL
with VHDL in this tutorial.
– Nios embedded processor
– GNUPro® Nios software development tools
■ Set up the Nios development board, as described in the
Nios Embedded Processor Quick Start Guide
■ Installed the ByteBlaster driver, as described in the
Quartus Installation and Licensing for PCs manual
■ Learned the basic features and operation of the Quartus
software, as described in the Quartus Tutorial manual.
Tutorial Files
This tutorial assumes that you create and save your files in a working
directory on the d: drive on your computer. If your working directory is on
another drive, substitute the appropriate drive name.
The Nios embedded processor installation creates the following
directories in the \altera\excalibur directory by default:
Directory Name: Description:
\nios_documentation Contains documentation for the Nios
embedded processor, Nios development
board, and GNUPro Toolkit.
\nios_sample_designs Contains Nios sample designs, including the
\reference_design_32_bit\reference_design
project that loads on the Nios development
board automatically upon power up. The
nios_system_module design you create in
this tutorial is based on the reference_design.
2 Altera CorporationNios Embedded Processor Hardware Tutorial
Design Entry
The following tutorial sections guide you through the steps needed to
create the nios_system_module project, and then explain how to create a
top-level BDF that contains the Nios system module. You create and
instantiate the Nios system module using the MegaWizard Plug-In
Manager.
Create a Quartus Project
1. Start the Quartus Software
In this section, you start the Quartus software and begin creating your
project.
To start the Quartus software, perform one of the following steps:
v Choose Programs > Altera > Quartus 2000.05 (Windows Start
menu).
or
v Type quartus r at the command prompt. The Quartus window
opens.
2. Create a Project
To create a new project, follow these steps:
1. Choose New (File menu). The Design Files tab of the New dialog box
appears automatically.
2. Click the Project Files tab.
Altera Corporation 3Nios Embedded Processor Hardware Tutorial
3. In the Project Files tab, select Project File.
4. Click OK. The New Project dialog box appears.
5. To specify the project directory, type
d:\Altera\Excalibur\nios_tutorial in the Project directory
box.
6. In the Project name box, type nios_system_module as the name
of the project.
7. In the Top-level design entity box, make sure
nios_system_module is specified as the name of the top-level
design entity of the project. See the following illustration:
8. Click OK. When the Quartus software asks you if you want to create
the new directory, click Yes.
The project is now created. The top-level design entity name appears
in the Hierarchies tab of the Project Navigator window. See the
following illustration:
Top-level design entity name
4 Altera CorporationNios Embedded Processor Hardware Tutorial
Create a Nios System Module
This section describes how to create the top-level BDF that contains a Nios
system module. After creating a design file, you can use the MegaWizard
Plug-In Manager to create the Nios embedded processor and configure
system peripherals. Next, you create the connections from the Nios
embedded processor and system peripherals to hardware components on
the Nios development board.
This section includes the following steps:
1. Create a new Block Design File (.bdf).
2. Create the Nios embedded processor.
3. Create & memory map system peripherals.
4. Configure system module settings.
5. Synthesize the design with LeonardoSpectrum software.
6. Enter input, output, bidirectional & primitive symbols.
7. Name the pins.
8. Connect the pins.
1. Create a New Block Design File
In this step you create a new BDF called nios_system_module.bdf. This file
is the top-level design entity of the nios_system_module project.
To create a new BDF, follow these steps:
1. Choose New (File menu). The Design Files tab of the New dialog box
appears automatically.
2. In the Design Files tab, select Block Diagram/Schematic File.
3. Click OK. A new Block Editor window appears.
4. Choose Save As (File menu).
5. Select the folder where you want to save the BDF. The Save As dialog
box should automatically display the project directory name,
d:\Altera\Excalibur\nios_tutorial, as the directory for saving the file.
Altera Corporation 5Nios Embedded Processor Hardware Tutorial
6. In the File name box, type nios_system_module as the name of
the BDF, if necessary.
7. Make sure Add file to current project is turned on.
8. Click Save. The file is saved and added to the project.
2. Create the Nios Embedded Processor
The MegaWizard Plug-In Manager allows you to create (or modify) design
files that contain custom variations of megafunctions, such as the Nios
system module. A complete Nios system module contains a Nios
embedded processor and its associated system peripherals. The
MegaWizard Plug-In Manager - Nios System Builder helps you specify
options for the system module easily. The wizard prompts you about the
values you want to set for parameters and which optional ports and
peripherals you want to use. Once the wizard generates the Nios system
module, you can instantiate it in the design file.
Follow these steps to create the Nios embedded processor in the
nios_system_module.bdf file:
1. Click the Selection Tool button on the toolbar. The Block Editor
toolbar has the following default toolbar buttons:
Selection Tool Text Tool
Symbol Tool Block Tool
Orthogonal Node Tool Orthogonal Bus Tool
Zoom Tool Full Screen
Find
Flip Horizontal Flip Vertical
Rotate Left 90
Rectangle Tool Oval Tool
Line Tool Arc Tool
2. Double-click an empty space in the Block Editor window. The
Symbol dialog box appears.
6 Altera CorporationNios Embedded Processor Hardware Tutorial
3. Click MegaWizard Plug-In Manager. The first page of the
MegaWizard Plug-In Manager is displayed, as shown in the
following illustration:
4. Under Which action do you want to perform?, select Create a new
custom megafunction variation and click Next. MegaWizard Plug-
In Manager page 2a appears.
5. In the Available Megafunctions list, make sure Altera Excalibur
Nios(tm) is selected.
6. Specify the following responses to the remaining wizard prompts in
MegaWizard Plug-In Manager page 2a:
Wizard Prompt: Response:
Which type of output file do Select Verilog HDL
you want to create?
What name do you want for Type d:\Altera\Excalibur\
the output file? nios_tutorial\nios32.v
7. Click Next. MegaWizard Plug-In Manager - Nios System Builder
page 3 appears.
8. In the Name box, leave the default name for the Nios embedded
processor, nios32_cpu.
9. To specify options for the Nios embedded processor, click Next.
MegaWizard Plug-In Manager - Nios page 1 appears.
Altera Corporation 7Nios Embedded Processor Hardware Tutorial
10. To specify that you want to use a 32-bit Nios embedded processor,
select Nios-32.
11. Click Next. MegaWizard Plug-In Manager - Nios page 2 appears.
12. Specify the following responses to the wizard prompts in
MegaWizard Plug-In Manager - Nios pages 2 through 4:
Wizard Prompt: Response:
Size of Address Bus Make sure 21 is selected
Register File Size Make sure 256 is selected
Internal Shifter Speed Make sure 7 is selected
Hardware-Assisted Turn on Include Multiply-step
Multiplication unit
13. In MegaWizard Plug-In Manager - Nios page 4, click Next.
MegaWizard Plug-In Manager - Nios page 5 appears.
14. To generate the Nios embedded processor with the options you
specified, click Finish. MegaWizard Plug-In Manager - Nios System
Builder page 4 appears.
3. Create & Memory Map System Peripherals
The Nios system peripherals allow the Nios embedded processor to
connect and communicate with internal logic in the APEX device, or
external hardware on the Nios development board. You can use the
MegaWizard Plug-In Manager - Nios System Builder to specify the name,
type, alignment, memory map addresses, and interrupts of the system
peripherals for your Nios system module.
1 These memory mappings ensure that the nios_system_module
design functions correctly on the Nios development board, and
allow you to run the software examples provided in the
\Cygwin\usr\altera\excalibur\nios-sdk\examples directory.
8 Altera CorporationNios Embedded Processor Hardware Tutorial
Create the boot_monitor_rom System Peripheral
The boot_monitor_rom on-chip ROM system peripheral is implemented
with Embedded System Blocks (ESBs) in the APEX device. To create the
boot_monitor_rom system peripheral, follow these steps:
1. In MegaWizard Plug-In Manager - Nios page 5, click Next.
MegaWizard Plug-In Manager - Nios System Builder page 4
appears, as shown in the following illustration:
2. In the New Peripheral Name box, type boot_monitor_rom.
3. In the Type list, select On-Chip ROM.
4. To specify ROM options, click Add. MegaWizard Plug-In Manager -
Nios Internal ROM page 1 appears.
5. Under ROM Size, select 512 as the number of half-words.
6. To specify the file that controls initialization of the Nios embedded
system processor, under ROM Input File type
reference_design_32_germs_monitor.mif or click Browse
Nios Library to select the file.
1 The Altera-provided reference_design_32_germs_monitor.mif
file contains the instructions necessary to initialize the Nios
embedded processor. This file is automatically executed when
Altera Corporation 9Nios Embedded Processor Hardware Tutorial
your design is downloaded to the APEX device. The assembly
language source code for this file is located in the \Cygwin\usr\
altera\excalibur\nios-sdk\otherstuff\germMon.s file.
7. Click Next. MegaWizard Plug-In Manager - Nios Internal ROM page
2 appears.
8. Click Finish to generate the boot_monitor_rom system peripheral
according to your specifications. The boot_monitor_rom system
peripheral name appears in MegaWizard Plug-In Manager - Nios
System Builder page 4, as shown in the following illustration:
Base Address cell
highlighted in yellow
9. To specify the base address of the boot_monitor_rom system
peripheral, click the Base Addr cell highlighted in yellow.
10. In the Base Addr cell, type 0x0 r. The end address 0x0003FF appears
in the End Addr column automatically.
1 You can simply type 0 r rather than 0x0 r and the
Quartus software displays the address in hexadecimal
notation automatically.
Create the ext_flash & ext_ram System Peripherals
The ext_flash and ext_ram off-chip memory system peripherals allow
the Nios embedded processor to interface with external memory
components on the Nios development board. To create the ext_flash
and ext_ram system peripherals, follow these steps:
10 Altera CorporationNios Embedded Processor Hardware Tutorial
1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type
ext_flash in the New Peripheral Name box.
2. In the Type list, select Memory Interface.
3. Click Add. MegaWizard Plug-In Manager page 1 appears.
4. Under Peripheral Type or Description, type Ext AM29LV800BB as
the peripheral type, as shown in the following illustration:
1 The Peripheral Type or Description box is for information
purposes only; therefore, you can type any name you want
in the box.
5. Click Next. MegaWizard Plug-In Manager page 2 appears.
6. Specify the following responses to the wizard prompts in
MegaWizard Plug-In Manager pages 2 through 7:
Wizard Prompt: Response:
Is your peripheral on-chip or Make sure Off-Chip is selected
off-chip?
Width of Data Bus Make sure 16 is specified
Width of Address Bus Type 19
Altera Corporation 11Nios Embedded Processor Hardware Tutorial
Wizard Prompt: Response:
Registered Chip-Select Option Make sure Use APEX Fast Output
Register for Chip-Select is turned
on
Wait-State Generation Select Fixed number of wait-
states
Read Wait States Type 8
Write Wait States Make sure 8 is specified
Interrupt Request Make sure Peripheral produces
Interrupt-request signal is
turned off
7. On MegaWizard Plug-In Manager page 6, click Next. MegaWizard
Plug-In Manager page 7 appears.
8. Click Finish to generate the ext_flash system peripheral. The
ext_flash system peripheral name appears in MegaWizard Plug-
In Manager - Nios System Builder page 4.
9. Click the Alignment cell for the ext_flash system peripheral and
select halfword from the list, as shown in the following illustration:
ext_flash system peripheral
Alignment cell
10. Click the Base Addr cell for the ext_flash system peripheral.
11. In the Base Addr cell, type 0x100000 r. The end address 0x1FFFFF
appears in the End Addr cell automatically.
12 Altera CorporationNios Embedded Processor Hardware Tutorial
12. Repeat steps 1 through 11 to create the ext_ram system peripheral
with the options listed in the following table:
Wizard Prompt: Response:
New Peripheral Name Type ext_ram
Type Select Memory Interface
Peripheral Type or Type Ext SRAM2xIDT71V016SA
Description
Is your peripheral on-chip or Make sure Off-Chip is selected
off-chip?
Width of Data Bus Type 32
Width of Address Bus Type 16
Registered Chip-Select Option Make sure Use APEX Fast Output
Register for Chip-Select is turned
on
Duplicate Chip-Select Select Two identical
Outputs
Wait-State Generation Select Fixed number of wait-
states
Read Wait States Type 0
Write Wait States Make sure 0 is specified
Interrupt Request Make sure Peripheral produces
Interrupt-request signal is
turned off
Alignment Make sure word is selected
Base Addr Type 0x40000
The system peripherals appear in MegaWizard Plug-In Manager -
Nios System Builder page 4, as shown in the following illustration:
Altera Corporation 13Nios Embedded Processor Hardware Tutorial
Create the button_pio, lcd_pio, led_pio & seven_seg_pio
System Peripherals
The button_pio, lcd_pio, led_pio, and seven_seg_pio parallel I/O
system peripherals allow the Nios embedded processor to interface with
external components, such as buttons, switches, the LCD display, and
LEDs on the Nios development board. To create the button_pio,
lcd_pio, led_pio, and seven_seg_pio system peripherals, follow
these steps:
1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type
button_pio in the New Peripheral Name box.
2. In the Type list, select Parallel I/O.
3. Click Add. MegaWizard Plug-In Manager - PIO page 1 appears.
1 If you have installed the Adobe Acrobat Reader software on your
PC, you can press F1 to display the data sheet for the PIO system
peripherals automatically.
4. Specify the following responses to the wizard prompts in
MegaWizard Plug-In Manager - PIO pages 1 through 2:
14 Altera CorporationNios Embedded Processor Hardware Tutorial
Wizard Prompt: Response:
How many bits of PIO would Type 12
you like (1-32)?
Type of pins Select Input pins only
Edge Capture Register Turn on Synchronously sample
inputs and capture. Select Any
Edge.
Interrupt source Turn on Generate irq input and
select Edge
5. In MegaWizard Plug-In Manager - PIO page 2, click Next.
MegaWizard Plug-In Manager - PIO page 3 appears.
6. To generate the button_pio system peripheral, click Finish. The
button_pio system peripheral name appears in MegaWizard Plug-
In Manager - Nios System Builder page 4.
7. Make sure word is specified in the Alignment cell for the
button_pio system peripheral.
8. Click the Base Addr cell for the button_pio system peripheral.
9. In the Base Addr cell, type 0x470 r. The end address of 0x00047F
appears in the End Addr cell automatically.
10. Click the IRQ cell for the button_pio system peripheral.
11. In the IRQ cell, type 19. The system peripherals appear in
MegaWizard Plug-In Manager - Nios System Builder page 4, as
shown in the following illustration:
Altera Corporation 15Nios Embedded Processor Hardware Tutorial
12. Repeat steps 1 through 11 to create three more parallel I/O system
peripherals—lcd_pio, led_pio, and seven_seg_pio—with the
options listed in the following tables.
Specify the following responses to the wizard prompts for the
lcd_pio system peripheral:
Wizard Prompt: Response:
New Peripheral Name Type lcd_pio
Type Select Parallel I/O
How many bits of PIO would Type 11
you like (1-32)?
Type of pins Select Tri-state (bidirectional)
pins
Edge Capture Register Make sure Synchronously
sample inputs and capture is
turned off
Interrupt source Make sure Generate irq input is
turned off
Alignment Make sure word is selected
Base Addr Type 0x480
IRQ N/A
Specify the following responses to the wizard prompts for the
led_pio system peripheral:
Wizard Prompt: Response:
New Peripheral Name Type led_pio
Type Select Parallel I/O
How many bits of PIO would Type 2
you like (1-32)?
Type of pins Select Output pins only
Alignment Make sure word is selected
Base Addr Type 0x460
IRQ N/A
16 Altera CorporationNios Embedded Processor Hardware Tutorial
Specify the following responses to the wizard prompts for the
seven_seg_pio system peripheral:
Wizard Prompt: Response:
New Peripheral Name Type seven_seg_pio
Type Select Parallel I/O
How many bits of PIO would Make sure 16 is specified
you like (1-32)?
Type of pins Select Output pins only
Alignment Make sure word is selected
Base Addr Type 0x420
IRQ N/A
The system peripherals appear in MegaWizard Plug-In Manager -
Nios System Builder page 4, as shown in the following illustration:
Create the uart1 System Peripheral
To create the uart1 RS-232 asynchronous receiver/transmitter UART
system peripheral, follow these steps:
1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type
uart1 in the New Peripheral Name box.
2. In the Type list, select Uart.
3. Click Add. MegaWizard Plug-In Manager - UART page 1 appears.
Altera Corporation 17Nios Embedded Processor Hardware Tutorial
1 If you have installed the Adobe Acrobat Reader software on your
PC, you can press F1 to display the data sheet for the UART
system peripheral automatically.
4. Specify the following responses to the wizard prompts in
MegaWizard Plug-In Manager - UART page 1:
Wizard Prompt: Response:
Input Clock Frequency Make sure 33333000 is specified
Baud Rate Select 115200 and make sure
Baud rate can be changed by
software is turned off.
Parity Make sure N is selected
Data Bits Make sure 8 is selected
Stop Bits Select 2
1 These UART specifications are compatible with the
nios-run terminal emulation program that you use later in
this tutorial.
5. On MegaWizard Plug-In Manager - UART page 1, click Next.
MegaWizard Plug-In Manager - UART page 2 appears.
6. To generate the uart1 system peripheral, click Finish. The uart1
system peripheral name appears in MegaWizard Plug-In Manager -
Nios System Builder page 4.
7. Make sure word is specified in the Alignment cell for the uart1
system peripheral.
8. Click the Base Addr cell for the uart1 system peripheral.
9. In the Base Addr cell, type 0x400 r. The end address of 0x00041F
appears in the End Addr cell automatically.
10. Click the IRQ cell for the uart1 system peripheral.
11. In the IRQ cell, type 16. The system peripherals appear in
MegaWizard Plug-In Manager - Nios System Builder page 4, as
shown in the following illustration:
18 Altera CorporationNios Embedded Processor Hardware Tutorial
Create the timer1 System Peripheral
To create the timer1 32-bit interval timer system peripheral, follow these
steps:
1. In MegaWizard Plug-In Manager - Nios System Builder page 4, type
timer1 in the New Peripheral Name box.
2. In the Type list, select Interval Timer.
3. Click Add. MegaWizard Plug-In Manager - TIMER page 1 appears.
1 If you have installed the Adobe Acrobat Reader software on your
PC, you can press F1 to display the data sheet for the timer
system peripheral automatically.
4. Click Next. MegaWizard Plug-In Manager - TIMER page 2 appears.
5. To generate the timer1 system peripheral, click Finish. The timer1
system peripheral name appears in MegaWizard Plug-In Manager -
Nios System Builder page 4.
6. Make sure word is specified in the Alignment cell for the timer1
system peripheral.
7. Click the Base Addr cell for the timer1 system peripheral.
8. In the Base Addr cell, type 0x440 r. The end address 0x00045F
appears in the End Addr cell automatically.
9. Click the IRQ cell for the timer1 system peripheral.
10. In the IRQ cell, type 15.
Altera Corporation 19Nios Embedded Processor Hardware Tutorial
You have now created all necessary system peripherals for the design, as
shown in the following illustration:
4. Configure System Module Settings
You must specify the reset address, vector table, and main program
memory in your design by configuring the system module settings. To
configure the system module settings, follow these steps:
1. On MegaWizard Plug-In Manager - Nios System Builder page 4,
click Next. MegaWizard Plug-In Manager - Nios System Builder
page 5 appears.
2. Under Reset Address, specify the following responses to the wizard
prompts:
Wizard Prompt: Response:
Peripheral Make sure boot_monitor_rom is
selected
Offset Make sure 0x0 is specified
20 Altera CorporationNios Embedded Processor Hardware Tutorial
3. Under Vector Table, specify the following responses to the wizard
prompts:
Wizard Prompt: Response:
Peripheral Make sure ext_ram is selected
Offset Make sure 0x0 is specified
4. Under Main Program Memory, make sure ext_ram is selected. See
the following illustration:
5. Click Next. MegaWizard Plug-In Manager - Nios System Builder
page 6 appears.
5. Synthesize the Design with
LeonardoSpectrum Software
Before you can compile the Nios system module with the Quartus software,
you must first synthesize the logic of the system module. You can use the
LeonardoSpectrum software, provided with the Quartus programmable
logic development tools, to synthesize the logic of the nios32 system
module and generate the nios32.edf file.
Altera Corporation 21Nios Embedded Processor Hardware Tutorial
1 To run the LeonardoSpectrum software or other OEM tools from
within the Quartus software, the location of the command-line
program for the tool must be specified in your system search
path, as described in the \Altera\Excalibur\
nios_documentation\faq_hdk.txt file.
To synthesize the design with LeonardoSpectrum software, follow these
steps:
1. On MegaWizard Plug-In Manager - Nios System Builder page 6,
select Leonardo Spectrum as the synthesis tool.
2. Click Next. MegaWizard Plug-In Manager - Nios System Builder
page 7 appears.
3. To synthesize the logic of the nios32 system module, click Finish.
The LeonardoSpectrum software runs within the MegaWizard Plug-
In Manager - Nios System Builder and begins to synthesize the
nios32 system module. As the LeonardoSpectrum software
synthesizes the design, it generates and displays various information
and warning messages in the wizard. Complete synthesis may
require up to 10 minutes or more. The wizard displays a message
when synthesis is complete, as shown in the following illustration:
4. When synthesis is complete, click Finish to exit the MegaWizard
Plug-In Manager and return to the Symbol dialog box. A preview of
the new nios32 symbol appears in the Symbol dialog box.
22 Altera CorporationNios Embedded Processor Hardware Tutorial
5. To instantiate the nios32 symbol in the BDF, click OK in the Symbol
dialog box. An outline of the nios32 symbol is attached to the
pointer.
6. To place the symbol, click an empty space in the Block Editor
window. The nios32 symbol is instantiated in the BDF, as shown in
the following illustration:
7. Choose Save (File menu).
6. Enter Input, Output, Bidirectional & Primitive
Symbols
To enter input, output, bidirectional, and primitive symbols, follow these
steps:
Altera Corporation 23Nios Embedded Processor Hardware Tutorial
1. Click the Symbol Tool button on the Block Editor toolbar (see step 1
on page 6 for an illustration of the toolbar buttons). The same
Symbol dialog box that you used to enter the nios32 symbol
appears. Note, however, that using the toolbar button opens this
dialog box with the Repeat-insert mode option turned on.
1 When Repeat-insert mode is turned on, an outline of the
selected symbol remains attached to the pointer,
regardless of how many times you click the mouse pointer,
allowing you to place multiple copies of the symbol easily.
Whenever you want to stop placing copies of a symbol, you
can press Esc or choose Cancel (right button pop-up
menu).
2. In the Symbol dialog box, in the Libraries list, click the + icon to
expand the d:\quartus\libraries folder, expand the primitives folder,
and then expand the pin folder.
3. In the pin folder, select the input primitive.
4. Click OK.
5. Click an empty space four times to insert a total of four INPUT
symbols on the left-hand side of the file. Symbols are automatically
named as pin_name in sequence. Press Esc.
6. Repeat steps 1 to 5 to insert and position a total of 13 OUTPUT pin
symbols and 2 BIDIR pin symbols in the file in the locations shown
in the following illustration:
24 Altera CorporationNios Embedded Processor Hardware Tutorial
7. Click the Symbol Tool button on the Block Editor toolbar. The
Symbol dialog box appears.
8. In the Symbol dialog box, in the Libraries list, click the + icon to
expand the d:\quartus\libraries folder, expand the primitives folder,
and then expand the other folder.
9. In the other folder, select the gnd primitive.
10. Click OK.
11. Click an empty space in the BDF to insert the GND symbol.
12. Click the Symbol Tool button on the Block Editor toolbar. The
Symbol dialog box appears.
13. In the Symbol dialog box, in the Libraries list, click the + icon to
expand the d:\quartus\libraries folder, expand the primitives folder,
and then expand the logic folder.
14. In the other folder, select the not primitive.
15. Click OK.
Altera Corporation 25Nios Embedded Processor Hardware Tutorial
16. Click an empty space in the BDF to insert the NOT symbol.
17. Choose Save (File menu).
7. Name the Pins
You can now name the input, output, and bidirectional pins. To name a
pin, follow these steps:
1. With the Selection Tool, double-click the first input pin symbol you
entered. The General tab of the Pin Properties dialog box appears
automatically. See the following illustration:
2. In the Pin name(s) box, type clk to replace the default name of the
first pin, that is, to replace pin_name.
3. Click OK.
4. Repeat steps 1 to 3 to rename each of the pins with the names listed
in the following tables.
26 Altera CorporationNios Embedded Processor Hardware Tutorial
Specify the following names for the INPUT pin symbols:
Pin Type: Rename As: Description
INPUT clk Clock signal
(already entered)
INPUT button_pio[11..0] Input from buttons and
switches
INPUT reset_n System reset
INPUT rxd uart1 receive signal
Specify the following names for OUTPUT and BIDIR pin symbols:
Pin Type: Rename As: Description
OUTPUT JP12_sel_n Enables the JP12
switchable 5V-
tolerant header used
with the LCD display
OUTPUT ext_sram_addr17 Output of SRAM
address 17 (Flash and
SRAM addr17 signals
connected to separate
APEX I/O pins)
BIDIR lcd_pio[10..0] LCD bidirectional
data signal
OUTPUT ext_addr[19..0] Off-chip shared
address signal
OUTPUT ext_be_n[3..0] Byte enables for off-
chip memory
BIDIR ext_data[31..0] Off-chip bidirectional
data signal
Altera Corporation 27Nios Embedded Processor Hardware Tutorial
Specify the following names for the remaining OUTPUT pin symbols:
Pin Type: Rename As: Description
OUTPUT ext_oe_n Shared off-chip
output enable
OUTPUT ext_ram_we_n SRAM write enable
OUTPUT ext_flash_we_n Flash memory
write enable
(Flash and SRAM
we_n signals
connected to
separate APEX I/O
signals)
OUTPUT seven_seg_pio[15..0] Output signal to
the seven segment
LED display
OUTPUT ext_ram_select_0_n SRAM chip select 0
OUTPUT ext_ram_select_1_n SRAM chip select 1
OUTPUT ext_flash_select_n Flash memory
chip select
OUTPUT txd uart1 transmit
signal
OUTPUT led_pio[1..0] Output signal to
the LEDs
5. Move the INPUT, OUTPUT, BIDIR, GND, and NOT symbols so they line
up with the appropriate ports and pinstubs, as shown in the
following illustration:
28 Altera CorporationNios Embedded Processor Hardware Tutorial
GND symbol NOT symbol
6. Choose Save (File menu).
8. Connect the Pins
After entering the inputs and outputs, you must connect them to the
appropriate ports on the Nios system module. To connect the pins and
primitives by drawing node and bus lines, follow these steps:
1. Click the Orthogonal Node Tool button on the toolbar (see step 1 on
page 6 for an illustration of the toolbar buttons).
2. Click the pinstub of the clk input pin to define the start of the node,
and then drag the pointer to draw a line that connects to the pinstub
of the clk port of the nios32 system module.
Altera Corporation 29Nios Embedded Processor Hardware Tutorial
1 When Use rubberbanding is turned on in the Block &
Symbol Editor General Options tab (Options command),
you can also draw node or bus lines by moving two
symbols together so that their borders and pinstubs touch.
When you move one of the symbols, a new line forms
automatically between the pinstubs of the two symbols.
3. Repeat steps 1 through 2 to make additional connections between
input and output pins and the nios32 system module ports shown
in the following table. You can also refer to Figure 1 on page 32.
Draw Node Line From: To:
INPUT pin clk clk port (already entered)
INPUT pin reset_n reset_n port
INPUT pin rxd rxd_to_the_uart1 port
OUTPUT pin JP12_sel_n Pinstub of GND symbol
OUTPUT pin ext_oe_n off_chip_shared_oe_n port
OUTPUT pin off_chip_shared_we_n port
ext_ram_we_n
OUTPUT pin Node connecting the
ext_flash_we_n ext_ram_we_n pin to the
off_chip_shared_we_n port
OUTPUT pin select_0_n_to_the_ext_ram
ext_ram_select_0_n port
OUTPUT pin select_1_n_to_the_ext_ram
ext_ram_select_1_n port
OUTPUT pin select_n_to_the_ext_flash
ext_flash_select_n port
OUTPUT pin txd txd_from_the_uart1 port
4. Click the Orthogonal Bus Tool button on the toolbar.
30 Altera CorporationNios Embedded Processor Hardware Tutorial
5. Click the pinstub of the button_pio[11..0] input pin to define
the start of a bus, and then drag the pointer to draw a line that
connects to the in_port_to_the_button_pio[11..0] port of
the nios32 system module.
6. Repeat steps 4 through 5 to make additional bus connections
between the INPUT, OUTPUT, and BIDIR pins and the nios32
system module ports shown in the following table. You can also refer
to Figure 1 on page 32.
Draw Bus Line From: To:
INPUT pin in_port_to_the_button_pio
button_pio[11..0] [11..0] port (already entered)
BIDIR pin bidir_port_to_and_from_the
lcd_pio[10..0] _lcd_pio[10..0] port
OUTPUT pin off_chip_shared_address
ext_addr[19..0] [19..0] port
OUTPUT pin off_chip_shared_be_n[3..0]
ext_be_n[3..0] port
BIDIR pin off_chip_shared_data_bus
ext_data[31..0] [31..0] port
OUTPUT pin out_port_from_the_seven_seg
seven_seg_pio[15..0] _pio[15..0] port
OUTPUT pin Output pinstub of the NOT primitive
led_pio[1..0]
NOT primitive input out_port_from_the_led_pio
pinstub [1..0] port
7. Click the Orthogonal Node Tool button on the toolbar.
8. To create a node that can be connected by name, draw a line from
the pinstub of the ext_sram_addr17 output pin to an empty space.
9. Click the Selection Tool button on the toolbar.
Altera Corporation 31Nios Embedded Processor Hardware Tutorial
10. Double-click the node line that connects to the pinstub of the
ext_sram_addr17 output pin. The General tab of the Node
Properties dialog box appears automatically.
11. In the Name box, type ext_addr17 as the name of the node.
12. Click OK. The name now appears above the node line. Adding this
name creates a logical connection between the ext_addr17 pin and
the ext_sram_addr17 output pin that is connected to the SRAM
device on the Nios development board.
13. Choose Save (File menu). The BDF is complete. See the following
illustration:
Figure 1. The Completed nios_system_module BDF
32 Altera CorporationNios Embedded Processor Hardware Tutorial
Compilation
The Quartus Compiler consists of a series of modules that check the design
for errors, synthesize the logic, fit the design into an Altera device, and
generate output files for simulation, timing analysis, and device
programming.
The following tutorial sections guide you through the steps necessary to
create Compiler settings, assign signals to device pins, specify EDA tool
settings, and compile the design.
Create Compiler Settings
You can create Compiler settings to control compilation processing. The
Compiler settings specify the compilation focus, the type of compilation to
perform, the device to target, and other options. This section includes the
following steps:
1. View the Compiler general settings.
2. Specify the device family and device.
1 The procedures below explain how to view and edit Compiler
settings using menu commands and dialog boxes. However, you
can also easily specify Compiler settings by following the steps in
the Compiler Settings Wizard (Processing menu).
1. View the Compiler General Settings
The General tab of the Compiler Settings dialog box allows you to select an
existing group of Compiler settings for use during compilation, define and
save a new group of Compiler settings, specify the compilation focus, or
delete existing settings.
To view the default Compiler general settings created for the current
project, follow these steps:
Altera Corporation 33Nios Embedded Processor Hardware Tutorial
1. Make sure that you are in Compile mode by selecting Compile Mode
(Processing menu).
2. Choose Compiler Settings (Processing menu). The General tab of
the Compiler Settings dialog box appears automatically.
At this point in the tutorial, the General tab displays only the default
Compiler general settings created by the Quartus software when the
project was initially created. These default settings are given the name of
the top-level design entity in the project, nios_system_module. See the
following illustration:
Specifies the
current
Compiler
settings.
Specifies the
hierarchical
path name of
the design
entity you want
to compile.
Shows the
existing
Compiler
settings for your
project.
2. Specify the Device Family & Device
The Chips & Devices tab of the Compiler Settings dialog box allows you to
select the family and device you want to target for compilation.
34 Altera CorporationNios Embedded Processor Hardware Tutorial
To select the device family and device, follow these steps:
1. In the Compiler Settings dialog box, click the Chips & Devices tab.
2. In the Family list, make sure APEX20KE is selected.
3. Under Target device, select Specific device selected in “Available
devices” list.
4. Under Show in “Available devices” list, select the following options:
a. In the Package list, select FBGA.
b. In the Pin count list, select 484.
c. In the Speed grade list, select -2. See the following illustration:
Identifies the
Compiler
settings you
are editing.
5. In the Available devices list, select EP20K200EFC484-2X.
Altera Corporation 35Nios Embedded Processor Hardware Tutorial
6. To accept the defaults for the remaining Compiler settings, click OK.
Assign Signals to Device Pins
During compilation, the Compiler assigns the logic of your design to
physical device resources. You can also make pin assignments to direct the
Compiler to assign signals in your design to specific pins in the target
device. Because the targeted APEX device is already mounted on the Nios
development board, you must assign the signals of the design to the
appropriate pins in the device.
The Quartus software provides several methods for making pin
assignments. You can assign pins individually with the Assignment
Organizer (Tools menu) or with the Pin Assignments dialog box, or you
can assign all necessary pins at once with a Tcl script. Because of the
number of pin assignments to be made in the tutorial, you can use the
Altera-provided pin_assign.tcl Tcl script to make the appropriate pin
assignments easily.
This session includes the following steps:
1. Assign pins with a Tcl script.
2. Verify the pin assignments.
1. Assign Pins with a Tcl Script
To make pin assignments with the Altera-provided pin_assign.tcl Tcl
script, follow these steps:
1. Make sure the Altera-provided pin_assign.tcl file is located in the
d:\Altera\Excalibur\nios_tutorial project directory.
2. To open the Quartus Tcl Console window, choose Auxiliary
Windows > Tcl Console (View menu). The Quartus Tcl Console
window appears. See the following illustration:
36 Altera CorporationNios Embedded Processor Hardware Tutorial
3. At the Quartus Tcl Console command prompt, type the following
command:
source pin_assign.tcl r
The Tcl script is executed and assigns all necessary pins. When the
assignments are complete, the assignment made message appears
in the Tcl Console window.
2. Verify the Pin Assignments
To verify the pin assignments, follow these steps.
1. Choose Compiler Settings (Processing menu). The General tab of
the Compiler Settings dialog box appears automatically.
2. Click the Chips & Devices tab.
3. Click Assign Pins. The Pin Assignments dialog box appears with the
new pin assignments listed in the Available Pins & Existing
Assignments list. See the following illustration:
Altera Corporation 37Nios Embedded Processor Hardware Tutorial
Lists the pin
assignments
made by the
Tcl script
4. When you are done viewing the pin assignments, click OK.
Specify Device, Programming & EDA Tool
Settings
Before compiling the design, you can specify options that control the use
of unused pins, optional programming file generation, and EDA tool
settings. This section includes the follow steps:
38 Altera CorporationNios Embedded Processor Hardware Tutorial
1. Reserve unused pins.
2. Specify optional programming files.
3. Specify EDA tool settings.
1. Reserve Unused Pins
To specify options for reserving unused pins, follow these steps:
1. In the Chips & Devices tab of the Compiler Settings dialog box, click
Device & Pin Options. The General tab of the Device & Pin Options
dialog box appears automatically.
2. Click the Unused Pins tab.
3. Under Reserve all unused pins, select As inputs, tri-stated.
2. Specify Optional Programming Files
By default, the Compiler always generates an SRAM Object File (.sof). The
Programmer uses an SOF to configure an APEX device with your design.
However, you can also direct the Compiler to generate other optional
programming files during compilation. For example, you can generate a
Hexadecimal (Intel-Format) Output File (.hexout) that can be used to
download your design to the user-configuration area of the flash memory
device provided on the Nios development board.
To specify optional programming files, follow these steps:
1. In the Device & Pin Options dialog box, click the Programming Files
tab.
2. Turn on Hexadecimal (Intel-Format) Output File (.hexout).
3. To accept the remaining defaults and save the device and pin
options, click OK.
4. In the Chips & Devices tab, click OK.
Altera Corporation 39Nios Embedded Processor Hardware Tutorial
3. Specify EDA Tool Settings
To specify the appropriate EDA tool settings for use when compiling a
design synthesized with the LeonardoSpectrum software, follow these
steps:
1. Choose EDA Tool Settings (Project menu). The EDA Tool Settings
dialog box appears.
2. Under Design entry/synthesis tool, select Leonardo Spectrum
(Level 1). See the following illustration:
3. Click OK.
Compile the Design
During compilation the Compiler locates and processes all design and
project files, generates messages and reports related to the current
compilation, and creates the SOF and any optional programming files.
40 Altera CorporationNios Embedded Processor Hardware Tutorial
To compile the nios_system_module design, follow these steps:
1. Choose Start Compilation (Processing menu).
The Compiler immediately begins to compile the
nios_system_module design entity, and any subordinate design
entities, using the nios_system_module Compiler settings. As the
design compiles, the Status window automatically displays, as a
percentage, the total compilation progress and the time spent in
each stage of the compilation. The results of the compilation are
updated in the Compilation Report window. The total compilation
time may require 20 minutes or more, depending on your system.
The Compiler may generate one or more of the following warning
messages that do not affect the outcome of your design:
Warning
messages
2. If you receive a message indicating that compilation was successful,
click OK to close the message box.
1 If the Compiler displays any error messages, you should
correct them in your design and recompile it until it is
error-free before proceeding with the tutorial. You can
select the message and choose Locate (right button pop-
up menu) to find its source(s), and/or choose Help (right
button pop-up menu) to display help on the message.
Altera Corporation 41Nios Embedded Processor Hardware Tutorial
Programming
After a successful compilation, the Quartus Compiler generates one or
more programming files that the Programmer can use to program or
configure a device. You can download configuration data directly into the
APEX device with the ByteBlasterMV communications cable connected to
the JTAG port on the Nios development board. You can also download
configuration data to a flash memory device on the Nios development
board over a serial port using a terminal emulation program. Then, you can
configure the APEX device using the data stored in flash memory.
Configure an APEX Device
Once you have properly connected and set up the MasterBlasterMV cable
to transmit configuration data over the JTAG port, you can configure the
APEX device on the Nios development board with your design.
To configure the APEX device on the Nios development board with the
nios_system_module design, perform the following steps:
1. Choose Open Programmer (Processing menu). The Programmer
window opens a blank Chain Description File (.cdf), as shown in the
following illustration:
Altera Corporation 43Nios Embedded Processor Hardware Tutorial
2. Choose Save As (File menu).
3. In the Save As dialog box, type nios_system_module.cdf in the
File name box.
4. Make sure that in the Save as type list, Chain Description File is
selected.
5. Click Save.
6. In the Mode list of the Programmer window, make sure JTAG is
selected.
7. Under Programming Hardware, click Setup. The Hardware Setup
dialog box opens.
8. In the Hardware Type list, select ByteBlasterMV.
9. In the Port list, select the port that is connected to the ByteBlasterMV
cable. Click OK.
10. Click Add File. The Select File dialog box appears.
11. Specify the nios_system_module.sof file in the File name box.
12. Click Open. The SOF is listed in the Programmer window.
44 Altera CorporationNios Embedded Processor Hardware Tutorial
13. In the Programmer window, turn on Program/Configure. See the
following illustration:
Program/Configure
turned on
14. On the Nios development board, make sure switch SW8 is in the
CONNECT position, and that switches SW9 and SW10 are in the
BYPASS position. Figure 2 illustrates the correct configuration of the
JTAG switches:
Figure 2. Nios Development Board JTAG Switch Configuration
CONNECT BYPASS
SW8
Apex JTAG
SW9
Max JTAG
SW10
PMC JTAG
Altera Corporation 45Nios Embedded Processor Hardware Tutorial
15. Click Start. The Programmer begins to download the configuration
data to the APEX device. The Progress field displays the percentage
of data that is downloaded. A message appears when the
configuration is complete.
When the design is successfully downloaded to the APEX device, the
following events occur:
■ The instructions specified in the boot_monitor_rom system
peripheral are executed. In this case, the
reference_designs_32_germs monitor.mif file (also known as the
“GERMS monitor”) located at 0x000 is executed. The GERMS
monitor performs the following system initialization tasks:
– Disables interrupts on the UART, timer, and switch PIO.
– Sets the Stack Pointer register to 0x080000.
– Examines two flash memory bytes at 0x14000C for executable
code.
– Determines the state of button SW4 on the Nios development
board.
■ When the GERMS monitor determines that the flash memory bytes
at 0x14000C contain n and i and that button SW4 is not pressed, it
executes a call to location 0x140000. By default, this call loads a
sample peripheral test program that you use later in this tutorial.
When the configuration is successfully completed, LED1 and LED2 are lit
on the Nios development board.
1 If you are unable to correctly configure the device, you can press
the RESET button on the Nios development board to reload the
factory default reference design and continue the tutorial.
Download the Design to Flash Memory
You can store configuration data in the flash memory device provided on
the Nios development board. This section describes how to use the GERMS
monitor to erase the user-configurable section of the flash memory device
46 Altera CorporationYou can also read
