Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers - MDPI
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electronics
Article
Design Trade-Offs in Common-Mode Feedback
Implementations for Highly Linear Three-Stage
Operational Transconductance Amplifiers
Joseph Riad 1, * , Sergio Soto-Aguilar 1 , Johan J. Estrada-López 2, * , Oscar Moreira-Tamayo 1
and Edgar Sánchez-Sinencio 1
1 Electrical and Computer Engineering Department, Texas A&M University, College Station, TX 77843, USA;
sergio.soto@tamu.edu (S.S.-A.); omoreira@tamu.edu (O.M.-T.); sanchez@ece.tamu.edu (E.S.-S.)
2 Faculty of Mathematics, Autonomous University of Yucatán, Mérida 97110, Yucatán, Mexico
* Correspondence: joseph.riad@tamu.edu (J.R.); johan.estrada@correo.uady.mx (J.J.E.-L.)
Abstract: Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits
to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern
amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With
multiple gain stages, different topologies for implementing CMFB are possible, whether using a
single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach
has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB
implementation topology evaluating performance in terms of stability, linearity, noise and common-
mode rejection. We present a detailed theoretical analysis, comparing the relative performance of
Citation: Riad, J.; Soto-Aguilar, S.;
two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our
Estrada-López, J.J.; Moreira-Tamayo,
analysis is then corroborated through a case study with full simulation results comparing the two
O.; Sánchez-Sinencio, E. Design
topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used
Trade-Offs in Common-Mode
as an example of a high-linearity OTA application, highlighting a 6 dB improvement in P1dB in the
Feedback Implementations for Highly
Linear Three-Stage Operational multi-loop implementation with respect to the single-loop case.
Transconductance Amplifiers.
Electronics 2021, 10, 991. https:// Keywords: common-mode feedback; common-mode rejection; linearity; three-stage OTA; stability;
doi.org/10.3390/electronics10090991 noise; active filter
Academic Editors: Paolo Colantonio
and Alessandro Cidronali
1. Introduction
Received: 15 March 2021
The Operational Transconductance Amplifier (OTA) is a fundamental building block
Accepted: 19 April 2021
in analog circuit design. It is designed to provide large voltage gain and to drive only
Published: 21 April 2021
capacitive loads, so it is characterized by a large output impedance [1]. The circuit symbol
of the OTA is shown in Figure 1. In many applications (such as active filters), the OTA has a
Publisher’s Note: MDPI stays neutral
negative feedback configuration applied to it, which improves the circuit’s bandwidth and
with regard to jurisdictional claims in
linearity, reduces noise and sensitivity to process variations [1]. However, those benefits
published maps and institutional affil-
rely on the OTA having high gain. The higher the OTA’s gain, the better the accuracy and
iations.
the rejection of unwanted noise.
As supply voltages continue to scale down in newer process technologies, achieving a
high gain with a simple two-stage OTA becomes more difficult and using the traditional
cascode configuration severely limits signal excursion. One solution to this problem is
Copyright: © 2021 by the authors.
to use multiple gain stages in cascade [2,3]. Moreover, high-precision applications ne-
Licensee MDPI, Basel, Switzerland.
cessitate the use of a fully-differential multi-stage OTA for the rejection of even-order
This article is an open access article
harmonic distortion and common-mode noise, which provide the added benefit of improv-
distributed under the terms and
ing dynamic range.
conditions of the Creative Commons
While differential signaling leads to improved linearity, it adds complexity to the
Attribution (CC BY) license (https://
circuit by requiring the use of a common-mode feedback (CMFB) loop to set the amplifier’s
creativecommons.org/licenses/by/
4.0/).
DC operating point and reject common-mode disturbances. The design of CMFB loops,
Electronics 2021, 10, 991. https://doi.org/10.3390/electronics10090991 https://www.mdpi.com/journal/electronicsElectronics 2021, 10, 991 2 of 31
therefore, forms an integral part of many applications and a careful approach is needed to
ensure they remain stable while being fast enough to reject common-mode disturbances
that lie within the OTA’s operational bandwidth [1,4].
An extra complication to the CMFB design problem in multi-stage OTAs is that there
are many different topological approaches to the implementation. For the three-stage
amplifier case, there are at least two different approaches as shown in Figure 1.
gmCM
−
Three-Stage OTA
CM Error Amplifier
− +
vin vout Vref
− + −
gm1 CM
H2 (s) H3 (s) AEA (s)
Sensor
+ − +
+ − vCM
vin vout
−
gmCM
(a) Single loop
gmCM2
−
Three-Stage OTA
CM Error Amplifier 2
− +
vin vout Vref2
− + −
gm1 CM
H2 (s) H3 (s) AEA2 (s)
Sensor 2
+ − +
+ − vCM2
vin vout
CM
gmCM1 Sensor 1 −
− −
gmCM2
+ vCM1
AEA1 (s)
− Vref1
CM Error Amplifier 1
(b) Multiple loops
Figure 1. Possible common-mode feedback (CMFB) implementations for a 3-stage amplifier. The blocks labeled H2 (s) and
H3 (s) together constitute the inner amplifier, including its compensation network.
As shown in Figure 1a, one possible solution is to have a single CMFB loop sensing the
output common-mode voltage and feeding back a common-mode current into the output
of the first stage. In the CMFB loop, a common-mode (CM) sensor is used to sense the
common-mode component of two voltages and then a CM error amplifier amplifies the
difference between this common-mode component and the reference voltage that we desireElectronics 2021, 10, 991 3 of 31
to set the CM component to. Thus, the CM negative feedback loop sets the common-mode
component of the voltages sensed by the CM sensor to the reference voltage input to the
CM error amplifier.
Another solution, shown in Figure 1b, is to use two CMFB loops, one to set the output
common-mode voltage by feeding back current into the output nodes and one to set the
output common-mode voltage of the H2 (s) stage and feeds back common-mode current
into the output of the first stage.
In the multi-stage amplifier literature, the topic of fully-differential OTA design is
rarely broached, in particular when it comes to the design trade-offs of different CMFB
approaches. If the intermediate gain stage is implemented in a fully-differential fashion,
several options for the CMFB loop implementation are available, such as using a single
loop that does not include all three stages [5] or using one loop per stage [6]. Such options
are not available for high-linearity applications since in those cases, a pseudo-differential
intermediate stage is used to improve signal swing and reduce distortion. The authors
of [7] implemented a two-loop switched-capacitor solution but do not go into details
concerning the trade-offs involved in the design of those CMFB loops. Some authors have
even achieved the impressive feat of designing four-stage fully differential amplifiers with
a single CMFB loop [4,8], but their approaches rely on the common-mode error amplifier
pole being at a much higher frequency than the differential loop bandwidth, which may not
be feasible in low-power amplifiers or high-frequency applications. Additionally, neither
work considers the impact of the CMFB loop design on amplifier linearity.
There is therefore a real need to approach these trade-offs in a systematic manner that
offers intuition to designers on the relative merits of different CMFB topologies. This is the
aim of this work.
At first glance, it seems that using multiple loops unnecessarily increases complexity
and power consumption, leading to the conclusion that the single-loop option is the better
solution. However, in this work we propose to investigate whether this original intuition
is justified. The performance of the two solutions will be qualitatively compared using
different metrics of performance. Among our findings, it is shown that using a single loop
can be challenging in terms of ensuring its stability and may end up being a worse option
in terms of linearity, area and power consumption.
Our analysis, both theoretical and with transistor-level simulations, proves the counter-
intuitive result that using multiple loops is actually better for performance, especially in
terms of linearity—arguably the most important metric that leads to the adoption of
fully-differential circuits in the first place.
This paper is organized as follows—in Section 2, an extensive theoretical analysis of the
two solutions is developed, based on the aspects of stability, linearity, noise performance
and common-mode rejection (CMR). In Section 3, a case study that implements both
solutions at the transistor level is simulated to confirm the results of the analysis. Particular
care is taken to ensure that both implementations consume the same amount of power and
share the same circuit architecture (except the CMFB loops) to ensure a fair comparison.
Also, an active-RC biquad low-pass filter is implemented, highlighting the linearity design
trade-off in a common application of multi-stage amplifiers. Section 4 provides a summary
discussion of the merits of each implementation. Finally, some conclusions are given.
2. Theoretical Comparison
In this section, the different performance aspects of the two designs are compared theo-
retically, with transistor-level simulation results confirming the analysis in the next section.
2.1. Stability
Since there are many different approaches to compensating the differential-mode loop
of a three-stage amplifier, it is important to evaluate the stability of the different CMFB
approaches in a manner that is agnostic to the underlying compensation scheme. For this
reason, we make use of the rate of closure (ROC) concept [9] to make qualitative argumentsElectronics 2021, 10, 991 4 of 31
about stability. In the transistor-level case study, the more traditional metrics of phase
margin (PM) and settling time are used.
For a negative feedback loop composed of two factors H (s) = X (s)Y (s), the ROC can
be obtained by plotting the magnitudes of X (s) and 1/Y (s) on the same set of axes. The
point of intersection of the two plots will be the unity-gain frequency of the loop and the
ROC is the absolute value of the difference between the slopes of the two curves at that
point (measured in dB/decade). The PM can then be approximated by
PM ' 180° − 4.5 × ROC. (1)
The only limitation on the use of the ROC approach is that ROC correlates to PM only
for minimum-phase systems, which means that any amplifiers whose transfer functions
contain right-half plane (RHP) zeros cannot be studied using this approach. However,
given their negative effects on stability, RHP zeros are usually avoided in the majority of
amplifiers [3,10,11].
It should be noted that, although ROC curves are most commonly used to express
negative feedback loops in terms of the feedforward factor A(s) and the feedback factor
β, the same principle applies for any factorization of the loop gain and the forthcoming
discussion, in fact, relies on a different factorization—the CM loop gain is expressed as the
product of the differential-mode gain and an algebraic factor that does not correspond to
physical circuit blocks.
2.1.1. Single Loop
Figure 2 shows the CM equivalent small-signal circuit model for the single-loop case.
In the figure, it is assumed that the transfer function of the CM voltage sensor is absorbed
into AEA (s). It is further assumed that Z1 includes the loading effect of the compensation
network used inside the inner amplifier’s stages, for which the transfer function is given
by H (s) = H2 (s) H3 (s).
gmCM AEA (s)
− −
gm1 gm2 gm3
vin
+ + − vo
Z1 Z2 Z3
H2 (s) H3 (s)
Figure 2. Small-signal model of the common-mode (CM) equivalent circuit for the single-loop design.
As a bare minimum, the transfer function AEA (s) has one pole and may be modeled by
AEA (0)
AEA (s) = , (2)
1 + s/ωCM
and this leads to the following formula for the loop gain of the CMFB loop:
LCM (s) = − gmCM Z1 · H (s) · AEA (s)
gm
= − ADM (s) · AEA (s) · CM , (3)
gm1Electronics 2021, 10, 991 5 of 31
where ADM (s) = gm1 Z1 H (s) denotes the differential-mode gain, a third-order transfer
function since the differential path has 3 stages. Since AEA (s) contains at least one pole,
the CMFB loop gain will be at least of the fourth order.
h gm
i −1
To study the ROC, we plot the magnitudes of ADM ( jω ) and AEA (s) · gmCM on
1
the same curve and their point of intersection represents the crossover frequency. This is
depicted in Figure 3.
|ADM (jω)|
ROC = 40 dB/dec
gmCM (jω) −1
AEA · gm1
(case 1)
−20 dB/dec gmCM (jω) −1
Magnitude (dB)
AEA · gm1
(case 2)
ωCM1
ωpd ωCM2
ω
20 dB/dec
−40 dB/dec
−60 dB/dec
ROC = 80 dB/dec
Figure 3. Rate of closure (ROC) curves for the single-loop design.
As seen in the figure, the worst-case ROC is 80 dB/decade, indicating a negative PM.
The PM can be improved by slowing down the CM error amplifier as demonstrated by the
dashed curve. This second case exhibits an ROC of 40 dB/decade which indicates a zero
PM (marginal stability). The phase margin can be improved to about 45° by aiming for a
ROC of 20 dB/decade, but the plot of Figure 3 indicates that achieving this ROC requires
slowing down the CM loop considerably, which can only be achieved in an efficient manner
by using compensation.
The suggested compensation scheme for this case is shown in Figure 4—adding
a compensation capacitor CCM with a buffer. This results in the CM amplifier’s pole
0 ) being defined primarily by the compensation capacitor instead of a much smaller
(ωCM
parasitic element. The buffer is added to isolate the differential mode loop and prevent
the compensation capacitor from loading it. Note that selecting the output of H2 for
compensation, takes advantage of the Miller effect to allow the use of a smaller physical
capacitor compared to using the input of H2 .
In this case, the CM loop gain is given by
0
LCM (s) = − gmCM Z1 · H (s) · AEA ( s ), (4)
where
0 AEA (0)
AEA (s) = 0 , (5)
1 + s/ωCM
showing the reduction in the CMFB error amplifier bandwidth due to the loading by the
compensation capacitor. We can thus write
gmCM 0
LCM (s) ' − · ADM (s) · AEA ( s ). (6)
gm1Electronics 2021, 10, 991 6 of 31
AEA (s)
gmCM gmEA (s)
− −
CCM ZEA
gm1 1
vin
+ H2 (s) H3 (s) vo
Z1
Figure 4. Small-signal model of the CM equivalent circuit for the compensated single-loop design.
As noted above, an ROC of about 20 dB/decade can be achieved by reducing the
bandwidth of the CMFB error amplifier. To quantify this reduction in bandwidth, we find
the critical point at which the ROC changes from 40 dB/decade to 20 dB/decade. This is
illustrated in Figure 5 where ω pd denotes the dominant pole of the differential-mode loop.
|ADM (jω)|
gmCM −1
A0EA (jω) · gm1
Magnitude (dB)
−20 dB/dec
20 dB/dec
f
0
ωCM
ωpd
−40 dB/dec
Figure 5. ROC curves for the compensated single-loop design.
From Figure 5, the following relationship holds
ADM (0) · AEA (0) · gmCM ω pd
20 log = 20 log 0
gm1 ωCM
0 gm1
ωCM = ω pd · , (7)
ADM (0) · AEA (0) · gmCM
which means that the bandwidth of the CMFB loop has to be considerably lower than
that of the differential loop as expected. Indeed, considering a differential loop DC gain
of 80 dB, we can see that the bandwidth of the common-mode loop may have to be up
to 4 orders of magnitudes lower than that of the differential loop. This implies that the
CMFB loop may fail to reject CM disturbances that lie within the bandwidth of interest
(differential loop bandwidth).Electronics 2021, 10, 991 7 of 31
2.1.2. Multiple Loops
In the case of multiple loops, Figure 6 shows the CM equivalent circuit.
gmCM1 AEA1 (s) AEA2 (s) gmCM2
− + + −
gm1 gm3
vin
+ H2 (s) − vo
Z1 Z3
Figure 6. Small-signal model of the CM equivalent circuit for the multi-loop design.
First, we note that the loops do not interact with each other, and therefore their stability
margins can be studied independently. It is straightforward to show that the loop gains are
given by
LCM1 (s) = − H2 (s) · AEA1 (s) · gmCM1 Z1
LCM2 (s) = − gmCM2 Z3 · AEA2 (s), (8)
with the error amplifier gains modeled by
AEAi (0)
AEAi (s) = , i = 1, 2. (9)
1 + s/ωCMi
Starting with the simpler self-loop at the output (LCM2 ), note that the poles are given
go
by CL +C3 and ωCM2 where go3 represents the output conductance of the third stage, CL
Miller
represents the load capacitance and CMiller represents the total loading effect of any part of
the Miller compensation network (used to compensate the differential-mode loop of the
core three-stage amplifier) that is connected to the output. If, by proper design, ωCM2 is set
at a high enough frequency, the self-loop is compensated by the load capacitance and does
not need additional compensation.
Turning our attention to LCM1 , we first start by noting that
N (s) 1
H2 (s) = H (s) · · , (10)
D (s) H3 (0)
where N (s) and D (s) are frequency-dependent factors needed to replace the poles and
zeros of H (s) with those of H2 (s). We can therefore express LCM1 (s) as follows:
gmCM1 N (s) 1
LCM1 (s) = − · ADM (s) · AEA1 (s) · · . (11)
gm1 D (s) H3 (0)
This means that, if the roots of N (s) and D (s) are positioned judiciously and H3 (0) is
large, an ROC that results in sufficient PM can be obtained without compensation.
As a concrete example, assume that the differential-mode amplifier is compensated
using single-Miller-capacitor compensation (SMC) [12] with a nulling resistor to cancel the
effect of the RHP zero as shown in Figure 7 (this figure is the half-circuit equivalent of the
differential-mode loop). In the figure,
1
Zi (s) = , (12)
goi + sCiElectronics 2021, 10, 991 8 of 31
where goi and Ci represent the output conductance and output capacitance of stage i
respectively, with C3 being the load capacitance CL .
RM CM
gm1 gm2 gm3
vin
+ + − vo
Z1 Z2 Z3
Figure 7. Example of the compensation strategy of the differential-mode loop.
The transfer function of the inner amplifier is therefore given by
gm2 gm3 1 + sC M R M + s2 gCmMgCm2
2 3
H (s) ' − · (13)
go2 go3 1 + s CM +CL + s2 (CM +CL )C2 + s3 CL CM C2 R M
go 3
go go 2 3
go go 2 3
and
gm2 1
H2 (s) = · , (14)
go2 1 + sC2
go 2
so that
s s
go3 1+ ω z1 1+ ω z2
H2 (s) = H (s) · · , (15)
gm3 1+ s
1+ s
|{z} ω p1 ω p2
1/H3 (0) | {z }
N (s)/D (s)
where
go3 1 1 gm2 gm3 R M
ω z1 ' ω z2 ' ω p1 ' ω p2 ' . (16)
C M + CL R M CCMM+CCL
L R M CM C2
This allows us to sketch the ROC curves as shown in Figure 8 with ω pd denoting the
dominant pole of the differential-mode gain and LCM1 0 denoting the factor LACM1
DM
so that
0
LCM1 = ADM /LCM1 . It can be seen that the ROC is 20 dB/decade, leading to a good PM.
In conclusion, the single-loop solution requires buffered Miller capacitor compensation
for the CMFB loop to ensure its stability without affecting the dynamics of the differential-
mode loop. On the other hand, the multi-loop solution can achieve stability for both
loops without requiring additional compensation capacitors. This result aligns well with
intuition because both loops in the multi-loop topology have lower order than the loop in
the single-loop topology and may therefore be stabilized simply by proper design, without
requiring bulky compensation capacitors.Electronics 2021, 10, 991 9 of 31
|ADM (jω)|
−20 dB/dec
L0CM1 (jω)
Magnitude (dB)
−20 dB/dec
−20 dB/dec
ωz2
ωpd ωp1 ωz1 ωp2
−40 dB/dec
f
−60 dB/dec
Figure 8. ROC curves for the first single-Miller-capacitor compensation (CMFB) loop with the SMC
compensation example.
2.2. Linearity
This section investigates the impact the CMFB loop generated harmonics can have in
the overall spectral purity of the differential signals. The following assumptions are made
to define the scope of the study:
• The common-mode error amplifier non-linearity converts the second harmonic of
the differential-mode voltage it senses into a common-mode so that its response is
given by
vcmEA = ACM vsens,cm + β CM v2sens,d , (17)
where vsens,cm is the common-mode component of the voltage sensed by the common-
mode error amplifier and vsens,d is the differential component of the same voltage.
• The common-mode amplifier will only respond to the components given in (17).
In other words, other harmonic components generated by intermediate stages are
negligible in the way they affect the common mode error amplifier.
In addition, the following conventions will be followed:
• We will assume that the input voltage produces differential- and common-mode
signals at the output of the first stage given by v1dm and v1cm , respectively.
• The non-linearity of the intermediate transconductance stages is modeled by:
i = gm v + β g v2 + γ g v3 , (18)
where v is the transcondutor’s input voltage and i its output current. β g and γg
represent, respectively, the second- and third-order transconductance gain coefficients.
Higher-order non-linear terms are neglected.
The main mechanism by which the CMFB sensor non-linearity affects the linearity of
the differential output signal can be described as follows [13]:
• The non-linearity of the CM error amplifier creates the second harmonic of the differ-
ential voltage it senses vsens,d which appears as a common-mode disturbance.Electronics 2021, 10, 991 10 of 31
• The non-linearity of the intermediate stages can mix this second harmonic with the
fundamental and create a third-order (and hence differential-mode) distortion.
Note that the non-linearity contribution of the CMFB loop can be reduced to nearly
zero if a resistive common-mode sensor is used. In this case, both CMFB loop implementa-
tions will yield similar linearity performance. However, this approach often requires the
use of large resistors to avoid loading the main gain stages. The large resistors introduce
noise, consume a substantial area and render the CMFB loop more difficult to stabilize
because they introduce a low-frequency pole at the input of the error amplifier, making
this approach impractical for many applications.
2.2.1. Single Loop
For this section, we solve the model of Figure 2 for the the differential output voltage
in terms of the other quantities under the assumptions and conventions stated above. The
buffered Miller capacitor compensation path is neglected in order to keep the analysis
simple, since it is not expected to significantly impact linearity.
The output differential voltage can be expressed as
v31d
vod = gm2 gm3 Z2 Z3 v1d + + f (v1d , v1cm ), (19)
HD3
where
1 γ3 Z2 g2 β β Z γ
2 m2
' 2Z1 Z22 Z32 β CM gm2 gm3 gmCM Z2 β 3 gm
2
2
+ β 2 m3 +
g + 2 3 2+ 2 (20)
HD3 4gm3 2gm3 4gm2
and HD3 denotes third-order harmonic distortion. We can see that the first two terms in (20)
are due to the non-linearity of the CMFB error amplifier converted into a differential-mode
distortion by the non-linearity in the intermediate stages.
2.2.2. Multiple Loops
Using the same assumptions as before, we get the following expression for HD3 of the
multi-loop solution:
!
2
gm γ3 Z22 gm
2
1 β β Z γ
2
= 2Z1 Z2 β CM1 gm2 gmCM1 Z2 β 3 2
+ β2 + 2
+ 2 3 2+ 2 . (21)
HD3 gm3 4gm3 2gm3 4gm2
Now, we consider only the non-linear terms of (20) and (21) contributed by the CM
error amplifier non-linearity (β CM ) and denote the resulting distortion factors by δ. We get
gm
δsingle = 2Av2 A2v3 Z1 Z2 β CM gmCM β 2 + Av2 β 3 2
gm3
gm
δmultiple = 2Av2 Z1 Z2 β CM1 gmCM1 β 2 + Av2 β 3 2
gm3
δmultiple 1 gm
= 2 · CM1 . (22)
δsingle Av3 gmCM
This ratio is much less than unity, which means that an amplifier using a single CMFB
loop will have more distortion than the one that uses multiple loops. Intuitively, this is
because in the single-loop case, the distortion products from the second stage are amplified
by the third stage inside the loop.
2.3. Noise
For noise analysis, we are interested in the contribution of the CMFB loops to differential-
mode noise. As a result, we do not consider the noise from the CM error amplifier as it
will appear as CM noise in the differential-mode loop and be rejected by the followingElectronics 2021, 10, 991 11 of 31
stages assuming good matching. It should also be noted that, when deriving the expression
for the input-referred differential-mode noise, noise shaping by the CM loop must not be
considered since it will only affect common-mode noise.
2.3.1. Single Loop
The only noise sources we need to consider in this case are gmCM and the buffers used
in the compensation of the CMFB loop. Note that there will be two such buffers with
uncorrelated noise contributions, which will not therefore appear as CM noise. The noise
2 . The input-referred
current from gmCM is simply referred to the input by dividing it by gm 1
noise of the buffer (v2buff ) is referred to the input by dividing it by the first and second stage
gains and we have the single-ended input-referred noise voltage given by
4kTγgmCM v2buff
v2nin,se = 2
+ , (23)
gm 1 [ gm1 Z1 (0) H2 (0)]2
where γ is the excess channel noise factor. Since the gain of the first two stages is large, we
can write
4kTγgmCM
v2nin,se ' 2
. (24)
gm 1
The differential noise voltage is simply twice the single-ended noise voltage [14]:
8kTγgmCM
v2nin,diff ' 2
. (25)
gm 1
2.3.2. Multiple Loops
By similar reasoning to the single-loop case, we will consider the gmCM1,2 transconduc-
tors as the only noise sources. The noise from gmCM1 is handled similarly to the single-loop
case. Meanwhile, the single-ended output noise voltage contribution of gmCM2 is given by
v2nout,se,CM2 = i2nCM2 · Z32 , (26)
so that the input-referred noise due to it alone is given by
i2nCM2 · Z32
v2nin,se,CM2 = . (27)
A2DM (0)
The input-referred differential noise voltage in this case will be given by
!
Z 2
8kTγ
v2nin,diff = 2 · gmCM1 + gmCM2 2 32 (28)
gm1 Z1 H (0)
and again, we may neglect the second component to find
8kTγgmCM1
v2nin,diff ' 2
. (29)
gm 1
The above analysis shows that, for equal power budgets, the two solutions exhibit
nearly identical noise performance. Indeed, as will be shown in the transistor-level imple-
mentation, gm1 and gmCM1 have the same bias current going through them (current re-use)
meaning that with the same device sizes and bias currents, the approximate input-referred
noise voltage expressions for the two solutions are identical.Electronics 2021, 10, 991 12 of 31
2.4. Common-Mode Disturbance Rejection
A very important metric for the performance of CMFB loops is their ability to reject
(attenuate) CM disturbances. This section will examine the CM rejection performance of
each solution in response to 2 types of CM disturbance:
• A CM current injected at the output nodes.
• A CM voltage imposed on the input nodes.
2.4.1. Single Loop
In the single-loop case, Figure 9 shows the two types of disturbances added to the
H (s) H (s) 0 is the gain of the error amplifier after CMFB
model with Gm (s) denoting 2 Z3 3 and AEA
loop compensation.
gmCM A0EA (s)
− −
gm1 Gm (s)
vi,CM vo,CM
+ −
Z1 Z3 iCM
Figure 9. CM equivalent small-signal model for CM disturbance rejection in the single-loop solution
In this case, we can prove that
vo,CM Z3
=− 0 (s) H (s) g
iCM 1 + AEA mCM Z1
vo,CM gm1 Z1 H (s)
= 0 (s) Z H (s)
vi,CM 1 + gmCM AEA 1
gm1
' 0 (s) . (30)
gmCM AEA
The above expressions show that CM disturbances at the output get rejected with the
full loop gain but since this loop gain is compensated, it will have a very low bandwidth. So
output common-mode disturbance rejection is possible only over a very narrow bandwidth
compared to the bandwidth of the differential-mode loop. On the other hand, a CM input
voltage disturbance will be rejected with only modest gain and very low bandwidth.
2.4.2. Multiple Loops
In this case, the disturbance model is shown in Figure 10 where Gm2 (s) and Gm3 (s)
denote, respectively H2 (s)/Z2 and H3 (s)/Z3 .
In this case, we have
vo,CM Z3
=−
iCM 1 + AEA2 (s) gmCM2
voCM gm1 Z1 H2 (s) H3 (s)
=
vi,CM [1 + gmCM1 AEA1 (s) H2 (s) Z1 ][1 + gmCM2 Z3 AEA2 (s)]
gm1 Gm3 (s)
' . (31)
gmCM1 gmCM2 AEA1 (s) AEA2 (s)Electronics 2021, 10, 991 13 of 31
We immediately see that the output disturbance gets rejected with a lower gain than
in the single-loop case but over a much wider bandwidth. In the case of an input voltage
disturbance, the disturbance gets rejected with a higher-gain than the single-loop case over
a comparable bandwidth. This assumes that the bandwidth of the second CM loop is high
enough that the rejection bandwidth will be fixed by loop 1. We therefore conclude that the
single-loop case is better at rejecting output CM disturbances at low-frequency while the
multi-loop case is better at rejecting input CM disturbances.
gmCM1AEA1 (s) AEA2 (s) gmCM2
− + + −
gm1 Gm2 (s) Gm3 (s)
vi,CM vo,CM
+ + −
Z1 Z2 Z3 icm
Figure 10. CM equivalent small-signal model for CM disturbance rejection in the multi-loop solution.
3. Design Case Study
In this section, transistor-level simulation results (using Spectre ®) for a 3-stage OTA
design will be used to corroborate the theoretical discussions of the previous section. First,
some performance specifications are established, then a specific topology is selected and
designed for both CMFB implementations. One of the main goals of the approach taken
here is to design both solutions with equal gain and similar power consumption. It is
important for both designs to have these similar metrics so that a fair comparison can be
made between the two solutions.
All the design and simulation results reported here reference a TSMC 180 nm CMOS
process with a power supply of 1.8 V.
3.1. Performance Specifications
The design of the OTA will target a unity-gain frequency (UGF) of 200 MHz, where
the desired application in this case is an active-RC filter with a 20 MHz corner frequency,
commonly used in multiple receiver standards [15]. The capacitive load is assumed to
be 1 pF.
As stated in [16–19], the design of 3-stage OTAs is best approached in the time domain.
With the target application in mind, we note that a 20 MHz signal has a period of 50 ns. As
a good rule of thumb, therefore, we will specify that the OTA’s settling time should not
exceed 5 ns (i.e., 10% of the signal’s period).
3.2. Topology Choice and System-Level Design
Since the chosen capacitive load is not large, choosing a topology with a compensated
inner amplifier will result in a more power-efficient design. In this case, the nested Gm -C
topology [20] is chosen. Figure 11 shows the half-circuit equivalent small-signal model of
this topology.
We denote the output conductance and parasitic capacitance of stage i by goi and Ci ,
respectively. Assuming gm f 1 = gm1 and gm f 2 = gm2 , the transfer function of the nested
Gm -C OTA is given by [20]:
gm1 gm2 gm3
H (s) = . (32)
go1 go2 go3 + sgm2 gm3 C M1 + s2 gm3 C M1 C M2 + s3 CL C M1 C M2
so that the non-dominant pole pair is defined by its natural frequency ω0 and quality factor
Q given byElectronics 2021, 10, 991 14 of 31
gm2 gm3
ω02 =
C M2 CL
r s
gm2 gm2 CL
Q= = · . (33)
C M2 ω0 gm3 C M2
C M1
C M2
gm1 g m2 g m3
vi vo
− + −
CL
gmf 2
gmf 1 −
−
Figure 11. Half-circuit equivalent small-signal model for the nested Gm -C topology.
ω0
Defining ω0 = GBW , we can generate a contour plot for the normalized settling time
in the ω0 − Q space via numerical simulations. The result is shown in Figure 12. Note that
the settling time definition used here is the time it takes for the amplifier’s output to reach,
and stay, within 1% of its final steady-state value.
Figure 12. Contour plots of the normalized settling time (TS · Gain-Bandwidth Product (GBW) to the
right) as a function of non-dominant pole parameters (ω0 and Q), final design point highlighted.
Assuming proper pole-zero cancellation and pole placement, the amplifier’s response
can be approximated as a one-pole system with UGF ≈ GBW. Since the intended UGF is
200 MHz, we need a normalized settling time of
Ts = Ts × UGF = 5 ns × 2π × 200 MHz = 2π. (34)
Using Figure 12 as reference, we thus choose ω0 = 2.3 and Q = √1 as highlighted in
2
the figure. From the expression for Q we haveElectronics 2021, 10, 991 15 of 31
gm2 1 gm2 Grad
= √ ⇒ = 2.04 . (35)
C M2 ω0 × GBW 2 C M2 s
Using this value and the equation for ω0 , we get gm3 = 4 mS. Assuming CM1 = 0.2 pF
and CM2 = 0.1 pF, we get gm1 = 251 µS and gm2 = 204 µS, thus completing the design process.
To verify the accuracy of this system design, a macromodel was built with ideal
voltage-controlled current sources and simulation results required gm2 to be adjusted
to obtain the required UGF and settling time. The final value chosen was 300 µS. Other
parameters of the design remained as chosen above. Figure 13 shows the Bode plot of
the gain of the simulated macromodel while Figure 14 shows its unit step response under
unity-gain feedback. It can be seen that the target specifications were met by this choice of
system parameter values.
Mag. (dB)/Phase (deg.)
100 Magnitude
Phase
0
−100 UGF = 200.9 MHz
PM = 54.5°
−200 GM = ∞
−300
10−3 10−2 10−1 100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
Figure 13. Transfer function of the macromodel of the designed Operational Transconductance
Amplifier (OTA).
1.2
1
Output voltage (V)
0.8
0.6
Ts = 4.11 ns
0.4
Overshoot = 13.94%
0.2
0
−0.2 Ts
0 2 4 6 8 10 12 14 16 18 20
t (ns)
Figure 14. Step response of the macromodel of the designed OTA.
3.3. Transistor-Level Amplifier
Figure 15 shows the transistor implementation of the fully-differential nested Gm -C
OTA with the transistors belonging to different sub-blocks highlighted. It should be noted
that Vx is set by the CMFB loop in both solutions while Vy is set by static bias in theElectronics 2021, 10, 991 16 of 31
single-loop solution and by the second CMFB loop in the multi-loop solution. Both Vx and
Vy are highlighted in red in the figure.
VDD
gm3 Vbp
gm3
M31 M23 M22 M11 M22 M23 M31
gm2 gm1 gm2
− +
− C M1 Vin Vin C M1 +
Vout Vout
C M2 M12 M12 C M2
Vy V bn Vx Vx Vbn Vy
M34 M33 M32 M24 M21 M13 M13 M21 M24 M32 M33 M34
gmf 2 gmf 2
VSS
VDD
Vbp
Mf 11
gmf 1
Mf 12 Mf 12
Mf 13 Mf 13
VSS
Figure 15. Schematic of the fully differential nested Gm -C OTA.
As can be seen in Figure 15, devices M12 implement gm1 while devices M13 implement
gmCM1 exploiting current re-use to limit power consumption and, as noted above, leading
the ratio gmCM1 /gm1 to be the same in both solutions. Devices M22 and M23 form a current
mirror that converts the polarity of gm2 to positive as required to make the feedback through
the Miller capacitor C M1 negative. Devices M33 supply extra current to the two output
branches to ensure that gm3 has the required value.
The design of the amplifier core was approached as follows:
1. Devices M12 were sized to provide the required gm1 with a VDSAT of 200 mV.
2. Devices M13 were sized to sink the current of M12 with a VDSAT of 150 mV.
3. The gm f 1 stage was sized in an identical fashion to the gm1 stage to ensure gm f 1 ≈ gm1 .
4. Devices M21 were sized to have the same current density as M13 with the ratio of
their sizing being gm2 /gm13 devices M24 were matched to M21 .
5. Devices M22 and M23 were sized equally to provide current mirroring with a VDSAT
of 200 mV.
6. Devices M31 were sized to have the same current density as M22 and M23 with the
ratio of their sizing being gm3 /gm23 .
7. Devices M32 were initially matched to M21 to ensure gm f 2 ≈ gm2 but ended up being
made larger to create a left-half-plane (LHP) zero and improve the phase margin in
the presence of an additional parasitic pole (due to resistive feedback when the core
amplifier is connected as a unity-gain inverting amplifier).
8. Devices M34 were matched to devices M f 13 .
9. Devices M33 were matched to M21 in current density. They were sized to provide
a current equal to the current required by M31 minus the currents supplied by M32
and M34 .
Table 1 shows the final device sizes in the core amplifier in accordance with the above
design procedure. Table 2 shows the capacitor values used with CCM denoting the capacitor
used to compensate the CMFB loop in the single-loop solution.Electronics 2021, 10, 991 17 of 31
Table 1. Device sizes for the schematic in Figure 15.
Device L (µm) W (µm) N (Number of Fingers) M (Device Multipliers)
M11 0.36 0.55 4 9
Mf11 0.36 0.55 4 9
M12 0.36 0.71 2 4
Mf12 0.36 0.71 2 4
M13 0.36 0.28 2 4
Mf13 0.36 0.28 2 4
M21 0.36 0.28 2 4
M22 0.36 0.67 2 4
M23 0.36 0.67 2 4
M24 0.36 0.28 2 4
M31 0.36 0.67 2 64
M32 0.36 0.28 2 28
M33 0.36 0.28 2 32
M34 0.36 0.28 2 4
Table 2. Capacitor values for the schematic in Figure 15. CCM denotes the capacitor used to compen-
sate the Common-Mode Feedback (CMFB) loop in the single-loop solution.
Capacitor Value (pF)
C M1 0.2
C M2 0.1
CCM 1
3.4. Design of Auxiliary Amplifiers
There are three different types of auxiliary amplifiers used in the design:
1. A low-gain CM error amplifier
2. A high-gain CM error amplifier (used to provide a high enough gain in the second
loop of the multi-loop solution to ensure good CM output voltage accuracy)
3. An amplifier configured in unity-gain feedback to act as a buffer for the compensation
of the CMFB loop in the single-loop solution.
Figure 16 shows the error amplifiers used in the single-loop solution and the first loop
of the multi-loop solution while Figure 17 shows the high-gain amplifier used in the second
loop of the multi-loop solution as well as the unity-gain buffer used to compensate the
CMFB loop of the single-loop solution. The basic underlying structure of all 4 amplifiers is
the same but their wiring is different. It should be noted that CM error amplifiers deliber-
ately use the differential-difference-amplifier-based CM voltage sensing (instead of using
resistors to sense the CM voltage) because this makes the CM sensor more non-linear [21]
and therefore emphasizes the effect of its non-linearity on the linearity of the amplifier.
The approach used to design these amplifiers was as follows:
1. Start by assigning a portion of the current budget to the error amplifier with respect to
the gmCM devices. For the case of the single-loop solution, the current through devices
Me2 –Me4 was the same as the current in M13 , for loop 1 of the multi-loop solution,
the same devices were made to carry only half of the current of M13 while in loop 2
1
they were made to carry 32 of the current of M33 so that the power consumption of
the two solutions remains the same.
2. Size the input devices Me2 –Me3 with the appropriate VDSAT . A value of 150 mV was
sufficient for the single-loop case and loop 2 of the multi-loop case because the
reference voltage is set at mid-supply. In the case of loop 1 of the multi-loop case, it
was necessary to reduce the VDSAT to 100 mV because the reference voltage driving
these devices (Vref1 ) is higher than mid-supply (∼1.1 V). Each of the Me2 devices is
half the size of the corresponding Me3 device.Electronics 2021, 10, 991 18 of 31
3. Finally, devices Me4 are matched in current density to the gmCM device they will be
connected to and sized in accordance with the ratio of currents chosen in the first step.
4. The buffer devices are sized identically to the single-loop error amplifier devices but
connected differently as shown in Figure 17.
VDD VDD
V bp Me1 V bp Me1
CM Voltage Sensor CM Voltage Sensor
+ − + −
Vsens Vsens Vref Vsens Vsens Vref1
Me2 Me2 Me3 Me2 Me2 Me3
Me4 Me4 Vx Me4 Me4
Vx
Error Amplifier VSS VSS
Error Amplifier
(a) (b)
Figure 16. Low-gain auxiliary amplifiers: (a) Error amplifier for the CMFB loop of the single-loop solution (b) Error amplifier
for the CMFB loop 1 of the multi-loop solution.
VDD
VDD
V bp Me1 Vbp Mbb1
CM Voltage Sensor
+
Vsens −
Vsens
Vin
Me2 Me2 Me3
Vref Mbb2 Mbb2
Vy
Vout
Me4 Me4
Mbb3 Mbb3
Error Amplifier VSS
(a) VSS
(b)
Figure 17. High-gain auxiliary amplifiers: (a) Error amplifier for CMFB loop 2 of the multi-loop solution (b) Amplifier in
unity-gain feedback acting as a buffer for the compensation of the CMFB loop in the single-loop solution.
Table 3 shows the final sizes of the devices used in the auxiliary amplifiers in the
single-loop solution while Table 4 shows those of the multi-loop solution.Electronics 2021, 10, 991 19 of 31
Table 3. Device sizes for the auxiliary amplifiers in the single-loop solution (Figures 16a and 17b).
Device L (µm) W (µm) N M
Me1 0.36 0.55 4 9
Me2 0.18 0.39 2 2
Me3 0.18 0.39 2 4
Me4 0.36 0.28 2 4
Mbb1 0.36 0.55 4 9
Mbb2 0.18 0.39 2 4
Mbb3 0.36 0.28 2 4
Table 4. Device sizes for the auxiliary amplifiers in the multi-loop solution (Figures 16b and 17a).
Device L (µm) W (µm) N M
Me1 (Loop 1) 0.36 0.55 4 4
Me2 (Loop 1) 0.18 0.27 2 4
Me3 (Loop 1) 0.18 0.27 2 8
Me4 (Loop 1) 0.36 0.28 2 2
Me1 (Loop 2) 0.36 0.55 4 4
Me2 (Loop 2) 0.18 0.34 2 1
Me3 (Loop 2) 0.18 0.34 2 2
Me4 (Loop 2) 0.36 0.28 2 2
3.5. Auxiliary Amplifier Responses
To make sure the auxiliary amplifiers work as expected, their transfer functions were
simulated separately and are shown in Figure 18. In all cases, the single-pole approximation
seems warranted except in the single-loop case where the amplifier has a RHP zero due to
the drain-to-gate device capacitance of devices Me2 in Figure 16a. This does not affect the
stability of the CMFB loop significantly and using a compensation capacitor to stabilize the
CMFB loop is still possible.
Single Loop Case Multi-Loop Case
−5
20
Mag. (dB)
Mag. (dB)
0
−10
−20
Loop 1
−15 Loop 2
−40
100 101 102 103 104 105 106 107 108 109 1010 1011 100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz) Frequency (Hz)
(a) (b)
0
−200
Phase (°)
Phase (°)
−50
−250 Loop 1
Loop 2
−100
−300
−150
−350
0 1 2 3 4 5 6 7 8 9 10 11
10 10 10 10 10 10 10 10 10 10 10 10 100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz) Frequency (Hz)
(c) (d)
Figure 18. Transfer function of the CMFB error amplifiers used in the different CMFB loops, (a) magnitude and (c) phase for
the single-loop case and (b) magnitude and (d) phase for the multi-loop case.Electronics 2021, 10, 991 20 of 31
3.6. Reference Voltage Generation
To generate the internal reference Vref1 shown in Figure 16b, recall that the M31 devices
were matched in current density to the M23 devices, so a good voltage level to set the
gates of M31 is the (common-mode) voltage at the gates of M23 . In order to generate this
CM voltage, a replica reference generator circuit (shown in Figure 19) was used. In the
0 devices have the same size as the M devices with the gate of each device
figure, the M21 21
connected to one of the two M21 devices. The M22 0 device, therefore, has twice the size of
the two M22 devices in the core amplifier.
VDD
0
M22 Vref1
0 0
To gate of M21 M21 M21 To gate of M21
VSS
Figure 19. Replica reference generator for the CM error amplifier of Figure 16b.
3.7. DC Simulation Results
Table 5 shows the DC simulation results for both solutions along with the specified
values in the initial design. It is seen that both solutions have very similar power budgets
and have achieved the specified values of all the transconductances (with the exception of
gm f 2 ) as discussed above.
Table 5. DC simulation results for the two solutions along with the target values specified in the
initial design.
Parameter Target Single-Loop Multi-Loop
gm1 (µS) 251 253.1 253.1
gm2 (µS) 300 320.1 321
gm3 (mS) 4 4.25 3.89
gm f 1 (µS) 251 253.2 253.2
gm f 2 (mS) 0.3 2.21 2.21
Vo,CM (V) 0.9 0.901 0.899
I_supply (mA) - 1.81 1.59
3.8. Differential Loop Response
For this test, the differential loop gain was simulated using two different methods—
with the amplifier in open loop (using ac analysis) and with the OTA configured as a
unity-gain inverting amplifier with 10 kΩ feedback resistors (using stability analysis). In
addition, the settling time performance is tested by injecting a 100 mV pp differential step
superimposed on top of the input common mode voltage to the OTA set in unity-gain
inverting amplifier configuration.
Figure 20 shows the transfer function of the differential-mode loop of the single-
loop solution. Along with measuring the loop gain in two ways as explained above, the
macromodel used for system design was fed with the parameter values obtained from
the DC simulation and the loop’s transfer function was plotted. It can be seen that the
macromodel is fairly accurate and sufficient for initial design. The discrepancy betweenElectronics 2021, 10, 991 21 of 31
the macromodel results and the simulation results at high frequencies is due to parasitic
capacitance and other second-order effects not accounted for in the macromodel. In addi-
tion, the closed-loop simulation takes into account the parasitic pole due to the interaction
of the feedback resistors with the amplifier’s input capacitance, which accounts for the
discrepancy between the two simulation methods.
100
Numerical model
Open-Loop
Mag. (dB)
Closed-loop
0
−100
100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(a)
0
Phase (°)
Numerical model
−200 Open-Loop
Closed-loop
−400
100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(b)
Figure 20. Transfer function of the differential loop in the single-loop solution (a) magnitude and
(b) phase.
Figure 21 shows the single-ended and differential output voltage in response to the
input step pulse for the single-loop solution. This confirms the stability of the loop assessed
from the frequency-domain results.
0.96
Differential Output voltage (mV)
100
0.94
Output voltage (V)
Vo+ 50
Vo−
0.92
0
0.9
0.88 −50
0.86 −100
0.84
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
t (ns) t (ns)
(a) (b)
Figure 21. Differential-mode step response of the single-loop solution: (a) single-ended output voltages and (b) differential
output voltage.
Figures 22 and 23 show the corresponding results for the multi-loop solution with
similar conclusions. Note that the single-ended output response exhibits some CM ringingElectronics 2021, 10, 991 22 of 31
because the CMFB loop has lower phase margin than its single-loop counterpart as will be
discussed in the next section.
Table 6 summarizes the simulation results for both cases. It can be seen that the
settling time specification was not met due to the parasitic pole not being accounted for in
the macromodel.
100
Numerical model
Open-Loop
Mag. (dB)
Closed-loop
0
−100
100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(a)
0
Phase (°)
Numerical model
−200 Open-Loop
Closed-loop
−400
100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(b)
Figure 22. Transfer function of the differential loop in the multi-loop solution (a) magnitude and
(b) phase.
0.96
Differential Output voltage (mV)
100
0.94
Vo+
Output voltage (V)
50
Vo−
0.92
0
0.9
0.88 −50
0.86
−100
0.84
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
t (ns) t (ns)
(a) (b)
Figure 23. Differential-mode step response of the multi-loop solution: (a) single-ended output voltages and (b) differential
output voltage.Electronics 2021, 10, 991 23 of 31
Table 6. Differential-mode results for both solutions.
Parameter Single-Loop Multi-Loop
DC gain (dB) 88.88 88.91
UGF (MHz) 167.01 165.75
PM (°) 51.27 50.79
GM (dB) 33.92 34.06
t+
s (ns) 9.90 10.06
t−
s (ns) 10.42 10.57
3.9. CMFB Loop Responses
The frequency- and time-domain responses for the CMFB loops were tested for both
solutions in an inverting amplifier configuration. The time-domain response was tested by
injecting 100 µA CM current step at the output nodes of the amplifier and measuring the
CM output voltage.
Figure 24 shows the frequency-domain results for the single-loop case while Figure 25
shows the results for the multi-loop case.
100
Mag. (dB)
50
0
−50
10−9 10−8 10−7 10−6 10−5 10−4 10−3 10−2 10−1 100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz)
(a)
200
Phase (°)
100
0
−100
10−9 10−8 10−7 10−6 10−5 10−4 10−3 10−2 10−1 100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz)
(b)
Figure 24. Transfer function of the CMFB loop in the single-loop case (a) magnitude and (b) phase.Electronics 2021, 10, 991 24 of 31
50
Mag. (dB)
0
Loop 1
−50 Loop 2
−100
10−9 10−8 10−7 10−6 10−5 10−4 10−3 10−2 10−1 100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(a)
200
Loop 1
Loop 2
Phase (°)
0
−200
−400
10−9 10−8 10−7 10−6 10−5 10−4 10−3 10−2 10−1 100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(b)
Figure 25. Transfer functions of the CMFB loops in the multi-loop case: (a) magnitude and (b) phase.
The transient responses (in both cases) for the loop settling after a CM current distur-
bance injected at the output are shown in Figure 26. It should be noted that, due to the
poorer PM of loop 2, the multi-loop case takes a slightly longer time to settle. In addition,
because of its lower DC gain, there is a 2 mV static error in the CM output voltage when
the CM disturbance is injected compared to normal conditions.
Falling Falling
905
Common-mode Output voltage (mV)
Common-mode Output voltage (mV)
Rising 899 Rising
904
898
903
897
902
901 896
900 895
899
894
898
893
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
t (ns) t (ns)
(a) (b)
Figure 26. CM step response (a) Single-loop and (b) Multi-loop.
Table 7 summarizes the results for all CMFB loops. It can be seen that the CMFB
loop in the single-loop case is more stable than loop 2 in the multi-loop case. If more
stability is needed in the multi-loop case, compensation capacitors can be added at the
expense of area and power (since the capacitors will have to be buffered as well). TheElectronics 2021, 10, 991 25 of 31
results, however, demonstrate that it is possible to design the multi-loop implementation
for stability without requiring the use of compensation capacitors, thereby saving on area
(and power, by avoiding the use of power-hungry voltage buffers).
Table 7. Common-mode results for both solutions.
Parameter Single-Loop Multi-Loop (Loop 1) Multi-Loop (Loop 2)
DC gain (dB) 88.91 29.23 48.62
UGF (MHz) 42.21 67.65 91.02
PM (°) 60.37 60.57 30.34
GM (dB) 22.11 ∞ ∞
3.10. Linearity
To assess the linearity of the amplifiers, a differential sinusoidal signal with 10 kHz
frequency was applied at the input (superimposed on the input CM level) with the amplifier
set in unity-gain feedback. The amplitude of the input signal was swept and the HD3
of the output differential voltage was obtained. The results are shown in Figure 27. The
results clearly confirm the theoretical analysis where the linearity of the multi-loop solution
is seen to be superior to the single-loop one. Given the fact that both amplifiers have
identical differential-mode loops (particularly, identical overdrive voltages for the input
stages), it stands to reason that the origin of the difference in performance lies in the
CMFB implementation.
3.11. Noise
To analyze noise performance, each OTA was put in inverting unity-gain feedback
configuration, the noise analysis was used to obtain the spectrum of the input-referred
noise. Figure 28 shows the noise spectra for both cases. The simulation results are in
agreement with analysis since the two spectra are virtually identical as illustrated by the
bottom curve of Figure 28 showing the difference between the single-loop spectrum and
the multi-loop spectrum.
65
60 Single-loop
Multi-loop
55
50
HD3 (dB)
45
40
35
30
25
20
15
100 200 300 400 500 600 700 800 900
Single-Ended Input Amplitude (mV)
Figure 27. Comparison of the linearity of the CMFB solutions.Electronics 2021, 10, 991 26 of 31
Input Noise (µV/ Hz)
Single-loop
√
60
Multi-loop
40
20
0
100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(a)
Noise Difference (nV/ Hz)
√
100
50
0
100 101 102 103 104 105 106 107 108 109 1010 1011
Frequency (Hz)
(b)
Figure 28. Input-referred noise for both cases: (a) input-referred noise and (b) difference between the
input-referred noise in the single-loop case and that in the multi-loop case.
3.12. CM Disturbance Rejection
To simulate the CM disturbance rejection, an AC input CM voltage disturbance is
injected to the amplifiers in a unity-gain inverting configuration, measuring the spectrum of
the output CM voltage. The result is shown in Figure 29 and confirms the theoretical results.
3.13. Filter Implementation
To demonstrate the impact of the CMFB loop implementation in a practical setting,
each of the OTAs was used to implement an active-RC biquad implementing the second-
order Butterworth low-pass function with a cut-off frequency of 20 MHz. Figure 30 shows
the final design of the biquad filter. The OTAs used in the biquad are both using the same
CMFB topology (i.e., 2 single-loop CMFB OTAs or 2 multi-loop CMFB OTAs).
−20
Mag. (dB)
−40
−60
Single-loop
Multi-loop
−80
100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz)
Figure 29. Input common-mode disturbance rejection.Electronics 2021, 10, 991 27 of 31
10 kΩ
7 kΩ
0.8 pF 0.8 pF
10 kΩ 10 kΩ
− +
Vin − − Vout
+ +
+ − − −
Vin + + Vout
10 kΩ 10 kΩ
0.8 pF 0.8 pF
7 kΩ
10 kΩ
Figure 30. Active-RC biquad implementing the Butterworth low-pass function with 20 MHz cut-
off frequency.
The biquad filter was simulated twice—once with the single-CMFB-loop OTA and once
with the multi-CMFB-loop OTA used for its implementation. Figure 31 shows the transfer
function of the transistor-level biquad circuit in both cases (both OTA implementation
cases exhibit the same biquad transfer function) compared to the ideal transfer function. It
is noted that the transistor-level implementations succeed in implementing the required
transfer function at low-to-moderate frequencies and the discrepancies present in high
frequencies are due to parasitics and second order effects.
0
Mag. (dB)
−50
Transistor-Level
Ideal
−100
100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz)
(a)
0 Transistor-Level
Ideal
−100
Phase (°)
−200
−300
100 101 102 103 104 105 106 107 108 109 1010
Frequency (Hz)
(b)
Figure 31. Biquad response. Transistor-level data is the same for both OTA implementations: (a) magni-
tude and (b) phase.Electronics 2021, 10, 991 28 of 31
As can be seen in Figure 27, the linearity improvement due to the use of multiple CMFB
loops only becomes apparent at large input amplitudes (i.e., in the strong non-linearity
regime). As such, the 1-dB compression point is used as a metric to emphasize the difference
in the filter’s linearity performance in the region of strong non-linearity. Compression
can be a significantly damaging effect on receiver chains (a common application of filters),
either as a result of the type of modulation employed or due to the presence of large
in-bandwidth blockers appearing from interference or transmitter leakage [22]. Figure 32
shows the compression point curves for both implementations.
20
Single-Loop
Multi-Loop
Output power (dBm)
Extrapolation Line
0
−20
−30 −20 −10 0 10 20
Input power (dBm)
Figure 32. 1-dB compression point curves for both biquad implementations.
The curves were obtained by stimulating the input with the two-tone test frequencies
of 4.5 MHz and 4.6 MHz [15]. The input amplitude was swept and the output amplitude at
the fundamental tone was observed (4.5 MHz). This method was used because the multi-
loop biquad implementation did not exhibit compression when the input was a single
tone. Likely due to the drop in gain inside the loop at the higher frequency harmonics.
From the curves, it can be seen that the input-referred 1-dB compression point (P1dB ) for
the single-loop biquad is 2.34 dBm while that for the multi-loop biquad is 9.08 dBm. This
demonstrates that the relative linearity merits of the multi-loop implementation still hold
when the OTA is used in a relevant high-linearity application. Table 8 shows a comparison
of the filter design with the state of the art. Although the results from this work are
simulation-only, the values of P1dB give additional context to understand the significant
performance advantage to be gained by choosing the proper CMFB implementation, while
remaining competitive in regards to power per pole.
Table 8. Comparison of filter metrics with state of the art.
This Work
Metric [23] [24] [25] [26]
Single-loop Multi-loop
Technology (nm) 65 65 130 180 180
Order-Type 4th BPF 4th LPF 4th LPF 5th LPF 2nd LPF
Topology Switched Gm-C Active-RC Active-RC Active-RC Active-RC
Filter’s f0 (MHz) 35 16 20 56 20
In-band IIP3 (dBm) 9.1 22.1 21 30.5 32.9
P1dB (dBm) −2.4 8 6.96 8 2.34 9.08
Power per pole (mW) 1.87 4.75 1.39 2.94 3.26 2.86You can also read
